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authorNicolai Hähnle <[email protected]>2018-07-02 18:50:48 +0200
committerMarek Olšák <[email protected]>2019-07-03 15:51:13 -0400
commit1666ee183e2dd0ae78cbec236315ad6328692589 (patch)
tree2390a9a50a316c490de7d56448c62a75088174b3 /src/gallium/drivers/radeonsi/si_texture.c
parent69c41fb8ff97bf31196a834e3e4086ae8247a9ff (diff)
radeonsi/gfx10: implement hardware MSAA resolve
MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile optimization that we use on gfx9 and earlier does not work. Be very explicit about how the swizzle mode of the temporary surface is selected. Acked-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_texture.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 37641c4a102..6e96b66f8a4 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -37,6 +37,7 @@
#include <inttypes.h>
#include "state_tracker/drm_driver.h"
#include "sid.h"
+#include "amd/addrlib/inc/addrinterface.h"
static enum radeon_surf_mode
si_choose_tiling(struct si_screen *sscreen,
@@ -310,6 +311,12 @@ static int si_init_surface(struct si_screen *sscreen,
if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
+ if (sscreen->info.chip_class >= GFX10 &&
+ (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
+ flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
+ surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
+ }
+
r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
array_mode, surface);
if (r) {