diff options
| author | Nicolai Hähnle <[email protected]> | 2018-07-02 18:50:48 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:13 -0400 |
| commit | 1666ee183e2dd0ae78cbec236315ad6328692589 (patch) | |
| tree | 2390a9a50a316c490de7d56448c62a75088174b3 /src/gallium/drivers | |
| parent | 69c41fb8ff97bf31196a834e3e4086ae8247a9ff (diff) | |
radeonsi/gfx10: implement hardware MSAA resolve
MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile
optimization that we use on gfx9 and earlier does not work.
Be very explicit about how the swizzle mode of the temporary surface is
selected.
Acked-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_blit.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_clear.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 7 |
3 files changed, 15 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 638f2ee4d24..9c6e3bc2c54 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -1109,6 +1109,12 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx, /* The next fast clear will switch to this mode to * get direct hw resolve next time if the mode is * different now. + * + * TODO-GFX10: This does not work in GFX10 because MSAA + * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes. + * In some cases we could change the swizzle of the + * destination texture instead, but the more general + * solution is to implement compute shader resolve. */ src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode; diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 60daff383cb..fa8ae5d2566 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -277,7 +277,8 @@ void vi_dcc_clear_level(struct si_context *sctx, static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex) { - if (tex->buffer.b.is_shared || + if (sscreen->info.chip_class >= GFX10 || + tex->buffer.b.is_shared || tex->buffer.b.b.nr_samples <= 1 || tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode) return; diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 37641c4a102..6e96b66f8a4 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -37,6 +37,7 @@ #include <inttypes.h> #include "state_tracker/drm_driver.h" #include "sid.h" +#include "amd/addrlib/inc/addrinterface.h" static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen, @@ -310,6 +311,12 @@ static int si_init_surface(struct si_screen *sscreen, if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; + if (sscreen->info.chip_class >= GFX10 && + (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) { + flags |= RADEON_SURF_FORCE_SWIZZLE_MODE; + surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X; + } + r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface); if (r) { |