diff options
| author | Kenneth Graunke <[email protected]> | 2014-02-10 15:09:22 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-02-19 15:39:41 -0800 |
| commit | 5476da79f87fed9173471d3ccd047b5ddeabecea (patch) | |
| tree | 385abf786334792742d82b5858ba0d9c24bd7817 | |
| parent | 80c4edfc27a4ee77d8fea4dd558a18f69df0579a (diff) | |
i965/fs: Implement FS_OPCODE_SET_SAMPLE_ID on Broadwell.
Largely cut and paste from Gen7; it works the same way.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 29 |
2 files changed, 32 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index eb9e1bf06a3..fd828f4d904 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -720,6 +720,10 @@ private: struct brw_reg index, struct brw_reg offset); void generate_mov_dispatch_to_flags(fs_inst *ir); + void generate_set_sample_id(fs_inst *ir, + struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1); void generate_set_simd4x2_offset(fs_inst *ir, struct brw_reg dst, struct brw_reg offset); diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp index ea1632091e8..dd067954e45 100644 --- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp @@ -596,6 +596,33 @@ gen8_fs_generator::generate_set_simd4x2_offset(fs_inst *ir, MOV_RAW(retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value); } +/** + * Do a special ADD with vstride=1, width=4, hstride=0 for src1. + */ +void +gen8_fs_generator::generate_set_sample_id(fs_inst *ir, + struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1) +{ + assert(dst.type == BRW_REGISTER_TYPE_D || dst.type == BRW_REGISTER_TYPE_UD); + assert(src0.type == BRW_REGISTER_TYPE_D || src0.type == BRW_REGISTER_TYPE_UD); + + struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW); + + unsigned save_exec_size = default_state.exec_size; + default_state.exec_size = BRW_EXECUTE_8; + + gen8_instruction *add = ADD(dst, src0, reg); + gen8_set_mask_control(add, BRW_MASK_DISABLE); + if (dispatch_width == 16) { + add = ADD(offset(dst, 1), offset(src0, 1), suboffset(reg, 2)); + gen8_set_mask_control(add, BRW_MASK_DISABLE); + } + + default_state.exec_size = save_exec_size; +} + void gen8_fs_generator::generate_code(exec_list *instructions) { @@ -975,7 +1002,7 @@ gen8_fs_generator::generate_code(exec_list *instructions) break; case FS_OPCODE_SET_SAMPLE_ID: - assert(!"XXX: Missing Gen8 scalar support for SET_SAMPLE_ID"); + generate_set_sample_id(ir, dst, src[0], src[1]); break; case FS_OPCODE_PACK_HALF_2x16_SPLIT: |