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authorRomain Dolbeau <[email protected]>2020-01-23 20:01:24 +0100
committerBrian Behlendorf <[email protected]>2020-01-23 11:01:24 -0800
commit35b07497c60701465a87aab48fc890a0bc502561 (patch)
treeded14fd0cfd7c3dd985617ae1d576d4e26c165a2 /module
parent1a69856034304e74b32fb372e89967e91989cafd (diff)
Add AltiVec RAID-Z
Implements the RAID-Z function using AltiVec SIMD. This is basically the NEON code translated to AltiVec. Note that the 'fletcher' algorithm requires 64-bits operations, and the initial implementations of AltiVec (PPC74xx a.k.a. G4, PPC970 a.k.a. G5) only has up to 32-bits operations, so no 'fletcher'. Reviewed-by: Brian Behlendorf <[email protected]> Signed-off-by: Romain Dolbeau <[email protected]> Closes #9539
Diffstat (limited to 'module')
-rw-r--r--module/zfs/Makefile.in7
-rw-r--r--module/zfs/vdev_raidz_math.c3
-rw-r--r--module/zfs/vdev_raidz_math_powerpc_altivec.c4337
-rw-r--r--module/zfs/vdev_raidz_math_powerpc_altivec_common.h688
4 files changed, 5035 insertions, 0 deletions
diff --git a/module/zfs/Makefile.in b/module/zfs/Makefile.in
index ef35ea5dd..129c83eb7 100644
--- a/module/zfs/Makefile.in
+++ b/module/zfs/Makefile.in
@@ -142,4 +142,11 @@ $(MODULE)-$(CONFIG_X86) += vdev_raidz_math_avx512bw.o
$(MODULE)-$(CONFIG_ARM64) += vdev_raidz_math_aarch64_neon.o
$(MODULE)-$(CONFIG_ARM64) += vdev_raidz_math_aarch64_neonx2.o
+$(MODULE)-$(CONFIG_PPC) += vdev_raidz_math_powerpc_altivec.o
+$(MODULE)-$(CONFIG_PPC64) += vdev_raidz_math_powerpc_altivec.o
+
+ifeq ($(CONFIG_ALTIVEC),y)
+$(obj)/vdev_raidz_math_powerpc_altivec.o: c_flags += -maltivec
+endif
+
-include @abs_top_builddir@/module/os/linux/zfs/Makefile
diff --git a/module/zfs/vdev_raidz_math.c b/module/zfs/vdev_raidz_math.c
index 294067e0f..14120e110 100644
--- a/module/zfs/vdev_raidz_math.c
+++ b/module/zfs/vdev_raidz_math.c
@@ -67,6 +67,9 @@ const raidz_impl_ops_t *raidz_all_maths[] = {
&vdev_raidz_aarch64_neon_impl,
&vdev_raidz_aarch64_neonx2_impl,
#endif
+#if defined(__powerpc__)
+ &vdev_raidz_powerpc_altivec_impl,
+#endif
};
/* Indicate that benchmark has been completed */
diff --git a/module/zfs/vdev_raidz_math_powerpc_altivec.c b/module/zfs/vdev_raidz_math_powerpc_altivec.c
new file mode 100644
index 000000000..feabfa5c0
--- /dev/null
+++ b/module/zfs/vdev_raidz_math_powerpc_altivec.c
@@ -0,0 +1,4337 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (C) 2019 Romain Dolbeau. All rights reserved.
+ * <[email protected]>
+ */
+
+#include <sys/isa_defs.h>
+#include <sys/types.h>
+
+#if defined(__powerpc__)
+#pragma GCC target("altivec")
+
+#include "vdev_raidz_math_powerpc_altivec_common.h"
+
+#define SYN_STRIDE 4
+
+#define ZERO_STRIDE 4
+#define ZERO_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_33_36()
+#define ZERO_D 0, 1, 2, 3
+
+#define COPY_STRIDE 4
+#define COPY_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_33_36()
+#define COPY_D 0, 1, 2, 3
+
+#define ADD_STRIDE 4
+#define ADD_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_33_36()
+#define ADD_D 0, 1, 2, 3
+
+#define MUL_STRIDE 4
+#define MUL_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_33_36()
+#define MUL_D 0, 1, 2, 3
+
+#define GEN_P_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_33_36()
+#define GEN_P_STRIDE 4
+#define GEN_P_P 0, 1, 2, 3
+
+#define GEN_PQ_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define GEN_PQ_STRIDE 4
+#define GEN_PQ_D 0, 1, 2, 3
+#define GEN_PQ_C 4, 5, 6, 7
+
+#define GEN_PQR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define GEN_PQR_STRIDE 4
+#define GEN_PQR_D 0, 1, 2, 3
+#define GEN_PQR_C 4, 5, 6, 7
+
+#define SYN_Q_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_Q_STRIDE 4
+#define SYN_Q_D 0, 1, 2, 3
+#define SYN_Q_X 4, 5, 6, 7
+
+#define SYN_R_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_R_STRIDE 4
+#define SYN_R_D 0, 1, 2, 3
+#define SYN_R_X 4, 5, 6, 7
+
+#define SYN_PQ_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_PQ_STRIDE 4
+#define SYN_PQ_D 0, 1, 2, 3
+#define SYN_PQ_X 4, 5, 6, 7
+
+#define REC_PQ_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36()
+#define REC_PQ_STRIDE 2
+#define REC_PQ_X 0, 1
+#define REC_PQ_Y 2, 3
+#define REC_PQ_T 4, 5
+
+#define SYN_PR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_PR_STRIDE 4
+#define SYN_PR_D 0, 1, 2, 3
+#define SYN_PR_X 4, 5, 6, 7
+
+#define REC_PR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36()
+#define REC_PR_STRIDE 2
+#define REC_PR_X 0, 1
+#define REC_PR_Y 2, 3
+#define REC_PR_T 4, 5
+
+#define SYN_QR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_QR_STRIDE 4
+#define SYN_QR_D 0, 1, 2, 3
+#define SYN_QR_X 4, 5, 6, 7
+
+#define REC_QR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36()
+#define REC_QR_STRIDE 2
+#define REC_QR_X 0, 1
+#define REC_QR_Y 2, 3
+#define REC_QR_T 4, 5
+
+#define SYN_PQR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_33_36()
+#define SYN_PQR_STRIDE 4
+#define SYN_PQR_D 0, 1, 2, 3
+#define SYN_PQR_X 4, 5, 6, 7
+
+#define REC_PQR_DEFINE() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_8_9() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36()
+#define REC_PQR_STRIDE 2
+#define REC_PQR_X 0, 1
+#define REC_PQR_Y 2, 3
+#define REC_PQR_Z 4, 5
+#define REC_PQR_XS 6, 7
+#define REC_PQR_YS 8, 9
+
+
+#include <sys/vdev_raidz_impl.h>
+#include "vdev_raidz_math_impl.h"
+
+DEFINE_GEN_METHODS(powerpc_altivec);
+DEFINE_REC_METHODS(powerpc_altivec);
+
+static boolean_t
+raidz_will_powerpc_altivec_work(void)
+{
+ return (kfpu_allowed()) && zfs_altivec_available();
+}
+
+const raidz_impl_ops_t vdev_raidz_powerpc_altivec_impl = {
+ .init = NULL,
+ .fini = NULL,
+ .gen = RAIDZ_GEN_METHODS(powerpc_altivec),
+ .rec = RAIDZ_REC_METHODS(powerpc_altivec),
+ .is_supported = &raidz_will_powerpc_altivec_work,
+ .name = "powerpc_altivec"
+};
+
+#endif /* defined(__powerpc__) */
+
+
+#if defined(__powerpc__)
+#if defined(_LITTLE_ENDIAN) && _LITTLE_ENDIAN
+/* BEGIN CSTYLED */
+const uint8_t
+__attribute__((aligned(256))) gf_clmul_mod_lt[4*256][16] = {
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0xf0, 0xe0, 0xd0, 0xc0, 0xb0, 0xa0, 0x90, 0x80,
+ 0x70, 0x60, 0x50, 0x40, 0x30, 0x20, 0x10, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 },
+ { 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0xe0, 0xc0, 0xa0, 0x80, 0x60, 0x40, 0x20, 0x00,
+ 0xe0, 0xc0, 0xa0, 0x80, 0x60, 0x40, 0x20, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10,
+ 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x00 },
+ { 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x10, 0x20, 0x70, 0x40, 0xd0, 0xe0, 0xb0, 0x80,
+ 0x90, 0xa0, 0xf0, 0xc0, 0x50, 0x60, 0x30, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x11, 0x12, 0x17, 0x14, 0x1d, 0x1e, 0x1b, 0x18,
+ 0x09, 0x0a, 0x0f, 0x0c, 0x05, 0x06, 0x03, 0x00 },
+ { 0x27, 0x27, 0x27, 0x27, 0x3a, 0x3a, 0x3a, 0x3a,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x00, 0x00, 0x00, 0x00 },
+ { 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40, 0x00,
+ 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x3c, 0x38, 0x34, 0x30, 0x2c, 0x28, 0x24, 0x20,
+ 0x1c, 0x18, 0x14, 0x10, 0x0c, 0x08, 0x04, 0x00 },
+ { 0x27, 0x27, 0x27, 0x27, 0x3a, 0x3a, 0x3a, 0x3a,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x00, 0x00, 0x00, 0x00 },
+ { 0x30, 0x60, 0x90, 0xc0, 0x70, 0x20, 0xd0, 0x80,
+ 0xb0, 0xe0, 0x10, 0x40, 0xf0, 0xa0, 0x50, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x33, 0x36, 0x39, 0x3c, 0x27, 0x22, 0x2d, 0x28,
+ 0x1b, 0x1e, 0x11, 0x14, 0x0f, 0x0a, 0x05, 0x00 },
+ { 0x3a, 0x3a, 0x3a, 0x3a, 0x27, 0x27, 0x27, 0x27,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x00, 0x00, 0x00, 0x00 },
+ { 0x20, 0x40, 0xe0, 0x80, 0xa0, 0xc0, 0x60, 0x00,
+ 0x20, 0x40, 0xe0, 0x80, 0xa0, 0xc0, 0x60, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x22, 0x24, 0x2e, 0x28, 0x3a, 0x3c, 0x36, 0x30,
+ 0x12, 0x14, 0x1e, 0x18, 0x0a, 0x0c, 0x06, 0x00 },
+ { 0x3a, 0x3a, 0x3a, 0x3a, 0x27, 0x27, 0x27, 0x27,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x00, 0x00, 0x00, 0x00 },
+ { 0xd0, 0xa0, 0x30, 0x40, 0x10, 0x60, 0xf0, 0x80,
+ 0x50, 0x20, 0xb0, 0xc0, 0x90, 0xe0, 0x70, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x2d, 0x2a, 0x23, 0x24, 0x31, 0x36, 0x3f, 0x38,
+ 0x15, 0x12, 0x1b, 0x1c, 0x09, 0x0e, 0x07, 0x00 },
+ { 0x53, 0x53, 0x4e, 0x4e, 0x69, 0x69, 0x74, 0x74,
+ 0x27, 0x27, 0x3a, 0x3a, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x78, 0x70, 0x68, 0x60, 0x58, 0x50, 0x48, 0x40,
+ 0x38, 0x30, 0x28, 0x20, 0x18, 0x10, 0x08, 0x00 },
+ { 0x53, 0x53, 0x4e, 0x4e, 0x69, 0x69, 0x74, 0x74,
+ 0x27, 0x27, 0x3a, 0x3a, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x70, 0xe0, 0x50, 0xc0, 0x30, 0xa0, 0x10, 0x80,
+ 0xf0, 0x60, 0xd0, 0x40, 0xb0, 0x20, 0x90, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x77, 0x7e, 0x65, 0x6c, 0x53, 0x5a, 0x41, 0x48,
+ 0x3f, 0x36, 0x2d, 0x24, 0x1b, 0x12, 0x09, 0x00 },
+ { 0x4e, 0x4e, 0x53, 0x53, 0x74, 0x74, 0x69, 0x69,
+ 0x27, 0x27, 0x3a, 0x3a, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00,
+ 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x66, 0x6c, 0x72, 0x78, 0x4e, 0x44, 0x5a, 0x50,
+ 0x36, 0x3c, 0x22, 0x28, 0x1e, 0x14, 0x0a, 0x00 },
+ { 0x4e, 0x4e, 0x53, 0x53, 0x74, 0x74, 0x69, 0x69,
+ 0x27, 0x27, 0x3a, 0x3a, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x90, 0x20, 0xf0, 0x40, 0x50, 0xe0, 0x30, 0x80,
+ 0x10, 0xa0, 0x70, 0xc0, 0xd0, 0x60, 0xb0, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x69, 0x62, 0x7f, 0x74, 0x45, 0x4e, 0x53, 0x58,
+ 0x31, 0x3a, 0x27, 0x2c, 0x1d, 0x16, 0x0b, 0x00 },
+ { 0x74, 0x74, 0x69, 0x69, 0x53, 0x53, 0x4e, 0x4e,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00,
+ 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x44, 0x48, 0x5c, 0x50, 0x74, 0x78, 0x6c, 0x60,
+ 0x24, 0x28, 0x3c, 0x30, 0x14, 0x18, 0x0c, 0x00 },
+ { 0x74, 0x74, 0x69, 0x69, 0x53, 0x53, 0x4e, 0x4e,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xb0, 0x60, 0x10, 0xc0, 0xf0, 0x20, 0x50, 0x80,
+ 0x30, 0xe0, 0x90, 0x40, 0x70, 0xa0, 0xd0, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x4b, 0x46, 0x51, 0x5c, 0x7f, 0x72, 0x65, 0x68,
+ 0x23, 0x2e, 0x39, 0x34, 0x17, 0x1a, 0x0d, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xa0, 0x40, 0x60, 0x80, 0x20, 0xc0, 0xe0, 0x00,
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+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xd8, 0x30, 0x08, 0xe0, 0x78, 0x90, 0xa8, 0x40,
+ 0x98, 0x70, 0x48, 0xa0, 0x38, 0xd0, 0xe8, 0x00 },
+ { 0x5f, 0xf9, 0x13, 0xb5, 0xc7, 0x61, 0x8b, 0x2d,
+ 0x72, 0xd4, 0x3e, 0x98, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0x70, 0xe0, 0x50, 0xc0, 0x30, 0xa0, 0x10, 0x80,
+ 0xf0, 0x60, 0xd0, 0x40, 0xb0, 0x20, 0x90, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xd7, 0x3e, 0x05, 0xec, 0x73, 0x9a, 0xa1, 0x48,
+ 0x9f, 0x76, 0x4d, 0xa4, 0x3b, 0xd2, 0xe9, 0x00 },
+ { 0x42, 0xe4, 0x0e, 0xa8, 0xda, 0x7c, 0x96, 0x30,
+ 0x72, 0xd4, 0x3e, 0x98, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00,
+ 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xc6, 0x2c, 0x12, 0xf8, 0x6e, 0x84, 0xba, 0x50,
+ 0x96, 0x7c, 0x42, 0xa8, 0x3e, 0xd4, 0xea, 0x00 },
+ { 0x42, 0xe4, 0x0e, 0xa8, 0xda, 0x7c, 0x96, 0x30,
+ 0x72, 0xd4, 0x3e, 0x98, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0x90, 0x20, 0xf0, 0x40, 0x50, 0xe0, 0x30, 0x80,
+ 0x10, 0xa0, 0x70, 0xc0, 0xd0, 0x60, 0xb0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xc9, 0x22, 0x1f, 0xf4, 0x65, 0x8e, 0xb3, 0x58,
+ 0x91, 0x7a, 0x47, 0xac, 0x3d, 0xd6, 0xeb, 0x00 },
+ { 0x78, 0xde, 0x34, 0x92, 0xfd, 0x5b, 0xb1, 0x17,
+ 0x6f, 0xc9, 0x23, 0x85, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00,
+ 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xe4, 0x08, 0x3c, 0xd0, 0x54, 0xb8, 0x8c, 0x60,
+ 0x84, 0x68, 0x5c, 0xb0, 0x34, 0xd8, 0xec, 0x00 },
+ { 0x78, 0xde, 0x34, 0x92, 0xfd, 0x5b, 0xb1, 0x17,
+ 0x6f, 0xc9, 0x23, 0x85, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0xb0, 0x60, 0x10, 0xc0, 0xf0, 0x20, 0x50, 0x80,
+ 0x30, 0xe0, 0x90, 0x40, 0x70, 0xa0, 0xd0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xeb, 0x06, 0x31, 0xdc, 0x5f, 0xb2, 0x85, 0x68,
+ 0x83, 0x6e, 0x59, 0xb4, 0x37, 0xda, 0xed, 0x00 },
+ { 0x65, 0xc3, 0x29, 0x8f, 0xe0, 0x46, 0xac, 0x0a,
+ 0x6f, 0xc9, 0x23, 0x85, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0xa0, 0x40, 0x60, 0x80, 0x20, 0xc0, 0xe0, 0x00,
+ 0xa0, 0x40, 0x60, 0x80, 0x20, 0xc0, 0xe0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xfa, 0x14, 0x26, 0xc8, 0x42, 0xac, 0x9e, 0x70,
+ 0x8a, 0x64, 0x56, 0xb8, 0x32, 0xdc, 0xee, 0x00 },
+ { 0x65, 0xc3, 0x29, 0x8f, 0xe0, 0x46, 0xac, 0x0a,
+ 0x6f, 0xc9, 0x23, 0x85, 0xea, 0x4c, 0xa6, 0x00 },
+ { 0x50, 0xa0, 0xb0, 0x40, 0x90, 0x60, 0x70, 0x80,
+ 0xd0, 0x20, 0x30, 0xc0, 0x10, 0xe0, 0xf0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0xf5, 0x1a, 0x2b, 0xc4, 0x49, 0xa6, 0x97, 0x78,
+ 0x8d, 0x62, 0x53, 0xbc, 0x31, 0xde, 0xef, 0x00 },
+ { 0xb7, 0x0c, 0xdc, 0x67, 0x61, 0xda, 0x0a, 0xb1,
+ 0x06, 0xbd, 0x6d, 0xd6, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x50, 0xa0, 0xb0, 0x40, 0x90, 0x60, 0x70, 0x80,
+ 0xd0, 0x20, 0x30, 0xc0, 0x10, 0xe0, 0xf0, 0x00 },
+ { 0xb7, 0x0c, 0xdc, 0x67, 0x61, 0xda, 0x0a, 0xb1,
+ 0x06, 0xbd, 0x6d, 0xd6, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0xf0, 0xe0, 0xd0, 0xc0, 0xb0, 0xa0, 0x90, 0x80,
+ 0x70, 0x60, 0x50, 0x40, 0x30, 0x20, 0x10, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x5f, 0xae, 0xbd, 0x4c, 0x9b, 0x6a, 0x79, 0x88,
+ 0xd7, 0x26, 0x35, 0xc4, 0x13, 0xe2, 0xf1, 0x00 },
+ { 0xaa, 0x11, 0xc1, 0x7a, 0x7c, 0xc7, 0x17, 0xac,
+ 0x06, 0xbd, 0x6d, 0xd6, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0xe0, 0xc0, 0xa0, 0x80, 0x60, 0x40, 0x20, 0x00,
+ 0xe0, 0xc0, 0xa0, 0x80, 0x60, 0x40, 0x20, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x4e, 0xbc, 0xaa, 0x58, 0x86, 0x74, 0x62, 0x90,
+ 0xde, 0x2c, 0x3a, 0xc8, 0x16, 0xe4, 0xf2, 0x00 },
+ { 0xaa, 0x11, 0xc1, 0x7a, 0x7c, 0xc7, 0x17, 0xac,
+ 0x06, 0xbd, 0x6d, 0xd6, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0x10, 0x20, 0x70, 0x40, 0xd0, 0xe0, 0xb0, 0x80,
+ 0x90, 0xa0, 0xf0, 0xc0, 0x50, 0x60, 0x30, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x41, 0xb2, 0xa7, 0x54, 0x8d, 0x7e, 0x6b, 0x98,
+ 0xd9, 0x2a, 0x3f, 0xcc, 0x15, 0xe6, 0xf3, 0x00 },
+ { 0x90, 0x2b, 0xfb, 0x40, 0x5b, 0xe0, 0x30, 0x8b,
+ 0x1b, 0xa0, 0x70, 0xcb, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40, 0x00,
+ 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x6c, 0x98, 0x84, 0x70, 0xbc, 0x48, 0x54, 0xa0,
+ 0xcc, 0x38, 0x24, 0xd0, 0x1c, 0xe8, 0xf4, 0x00 },
+ { 0x90, 0x2b, 0xfb, 0x40, 0x5b, 0xe0, 0x30, 0x8b,
+ 0x1b, 0xa0, 0x70, 0xcb, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0x30, 0x60, 0x90, 0xc0, 0x70, 0x20, 0xd0, 0x80,
+ 0xb0, 0xe0, 0x10, 0x40, 0xf0, 0xa0, 0x50, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x63, 0x96, 0x89, 0x7c, 0xb7, 0x42, 0x5d, 0xa8,
+ 0xcb, 0x3e, 0x21, 0xd4, 0x1f, 0xea, 0xf5, 0x00 },
+ { 0x8d, 0x36, 0xe6, 0x5d, 0x46, 0xfd, 0x2d, 0x96,
+ 0x1b, 0xa0, 0x70, 0xcb, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0x20, 0x40, 0xe0, 0x80, 0xa0, 0xc0, 0x60, 0x00,
+ 0x20, 0x40, 0xe0, 0x80, 0xa0, 0xc0, 0x60, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x72, 0x84, 0x9e, 0x68, 0xaa, 0x5c, 0x46, 0xb0,
+ 0xc2, 0x34, 0x2e, 0xd8, 0x1a, 0xec, 0xf6, 0x00 },
+ { 0x8d, 0x36, 0xe6, 0x5d, 0x46, 0xfd, 0x2d, 0x96,
+ 0x1b, 0xa0, 0x70, 0xcb, 0xd0, 0x6b, 0xbb, 0x00 },
+ { 0xd0, 0xa0, 0x30, 0x40, 0x10, 0x60, 0xf0, 0x80,
+ 0x50, 0x20, 0xb0, 0xc0, 0x90, 0xe0, 0x70, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x7d, 0x8a, 0x93, 0x64, 0xa1, 0x56, 0x4f, 0xb8,
+ 0xc5, 0x32, 0x2b, 0xdc, 0x19, 0xee, 0xf7, 0x00 },
+ { 0xe4, 0x5f, 0x92, 0x29, 0x08, 0xb3, 0x7e, 0xc5,
+ 0x21, 0x9a, 0x57, 0xec, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x28, 0xd0, 0xd8, 0x20, 0xc8, 0x30, 0x38, 0xc0,
+ 0xe8, 0x10, 0x18, 0xe0, 0x08, 0xf0, 0xf8, 0x00 },
+ { 0xe4, 0x5f, 0x92, 0x29, 0x08, 0xb3, 0x7e, 0xc5,
+ 0x21, 0x9a, 0x57, 0xec, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x70, 0xe0, 0x50, 0xc0, 0x30, 0xa0, 0x10, 0x80,
+ 0xf0, 0x60, 0xd0, 0x40, 0xb0, 0x20, 0x90, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x27, 0xde, 0xd5, 0x2c, 0xc3, 0x3a, 0x31, 0xc8,
+ 0xef, 0x16, 0x1d, 0xe4, 0x0b, 0xf2, 0xf9, 0x00 },
+ { 0xf9, 0x42, 0x8f, 0x34, 0x15, 0xae, 0x63, 0xd8,
+ 0x21, 0x9a, 0x57, 0xec, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00,
+ 0x60, 0xc0, 0x20, 0x80, 0xe0, 0x40, 0xa0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x36, 0xcc, 0xc2, 0x38, 0xde, 0x24, 0x2a, 0xd0,
+ 0xe6, 0x1c, 0x12, 0xe8, 0x0e, 0xf4, 0xfa, 0x00 },
+ { 0xf9, 0x42, 0x8f, 0x34, 0x15, 0xae, 0x63, 0xd8,
+ 0x21, 0x9a, 0x57, 0xec, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x90, 0x20, 0xf0, 0x40, 0x50, 0xe0, 0x30, 0x80,
+ 0x10, 0xa0, 0x70, 0xc0, 0xd0, 0x60, 0xb0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x39, 0xc2, 0xcf, 0x34, 0xd5, 0x2e, 0x23, 0xd8,
+ 0xe1, 0x1a, 0x17, 0xec, 0x0d, 0xf6, 0xfb, 0x00 },
+ { 0xc3, 0x78, 0xb5, 0x0e, 0x32, 0x89, 0x44, 0xff,
+ 0x3c, 0x87, 0x4a, 0xf1, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00,
+ 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x14, 0xe8, 0xec, 0x10, 0xe4, 0x18, 0x1c, 0xe0,
+ 0xf4, 0x08, 0x0c, 0xf0, 0x04, 0xf8, 0xfc, 0x00 },
+ { 0xc3, 0x78, 0xb5, 0x0e, 0x32, 0x89, 0x44, 0xff,
+ 0x3c, 0x87, 0x4a, 0xf1, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0xb0, 0x60, 0x10, 0xc0, 0xf0, 0x20, 0x50, 0x80,
+ 0x30, 0xe0, 0x90, 0x40, 0x70, 0xa0, 0xd0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x1b, 0xe6, 0xe1, 0x1c, 0xef, 0x12, 0x15, 0xe8,
+ 0xf3, 0x0e, 0x09, 0xf4, 0x07, 0xfa, 0xfd, 0x00 },
+ { 0xde, 0x65, 0xa8, 0x13, 0x2f, 0x94, 0x59, 0xe2,
+ 0x3c, 0x87, 0x4a, 0xf1, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0xa0, 0x40, 0x60, 0x80, 0x20, 0xc0, 0xe0, 0x00,
+ 0xa0, 0x40, 0x60, 0x80, 0x20, 0xc0, 0xe0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x0a, 0xf4, 0xf6, 0x08, 0xf2, 0x0c, 0x0e, 0xf0,
+ 0xfa, 0x04, 0x06, 0xf8, 0x02, 0xfc, 0xfe, 0x00 },
+ { 0xde, 0x65, 0xa8, 0x13, 0x2f, 0x94, 0x59, 0xe2,
+ 0x3c, 0x87, 0x4a, 0xf1, 0xcd, 0x76, 0xbb, 0x00 },
+ { 0x50, 0xa0, 0xb0, 0x40, 0x90, 0x60, 0x70, 0x80,
+ 0xd0, 0x20, 0x30, 0xc0, 0x10, 0xe0, 0xf0, 0x00 },
+ { 0x69, 0x69, 0x74, 0x74, 0x4e, 0x4e, 0x53, 0x53,
+ 0x3a, 0x3a, 0x27, 0x27, 0x1d, 0x1d, 0x00, 0x00 },
+ { 0x05, 0xfa, 0xfb, 0x04, 0xf9, 0x06, 0x07, 0xf8,
+ 0xfd, 0x02, 0x03, 0xfc, 0x01, 0xfe, 0xff, 0x00 }
+};
+/* END CSTYLED */
+#else
+/* BEGIN CSTYLED */
+const uint8_t
+__attribute__((aligned(256))) gf_clmul_mod_lt[4*256][16] = {
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
+ 0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
+ { 0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0,
+ 0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
+ { 0x00, 0x30, 0x60, 0x50, 0xc0, 0xf0, 0xa0, 0x90,
+ 0x80, 0xb0, 0xe0, 0xd0, 0x40, 0x70, 0x20, 0x10 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09,
+ 0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11 },
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+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xf9, 0xf2, 0x0b, 0xe4, 0x1d, 0x16, 0xef,
+ 0xc8, 0x31, 0x3a, 0xc3, 0x2c, 0xd5, 0xde, 0x27 },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xec, 0x57, 0x9a, 0x21,
+ 0xd8, 0x63, 0xae, 0x15, 0x34, 0x8f, 0x42, 0xf9 },
+ { 0x00, 0xa0, 0x40, 0xe0, 0x80, 0x20, 0xc0, 0x60,
+ 0x00, 0xa0, 0x40, 0xe0, 0x80, 0x20, 0xc0, 0x60 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xfa, 0xf4, 0x0e, 0xe8, 0x12, 0x1c, 0xe6,
+ 0xd0, 0x2a, 0x24, 0xde, 0x38, 0xc2, 0xcc, 0x36 },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xec, 0x57, 0x9a, 0x21,
+ 0xd8, 0x63, 0xae, 0x15, 0x34, 0x8f, 0x42, 0xf9 },
+ { 0x00, 0xb0, 0x60, 0xd0, 0xc0, 0x70, 0xa0, 0x10,
+ 0x80, 0x30, 0xe0, 0x50, 0x40, 0xf0, 0x20, 0x90 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xfb, 0xf6, 0x0d, 0xec, 0x17, 0x1a, 0xe1,
+ 0xd8, 0x23, 0x2e, 0xd5, 0x34, 0xcf, 0xc2, 0x39 },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
+ 0xff, 0x44, 0x89, 0x32, 0x0e, 0xb5, 0x78, 0xc3 },
+ { 0x00, 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40,
+ 0x00, 0xc0, 0x80, 0x40, 0x00, 0xc0, 0x80, 0x40 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xfc, 0xf8, 0x04, 0xf0, 0x0c, 0x08, 0xf4,
+ 0xe0, 0x1c, 0x18, 0xe4, 0x10, 0xec, 0xe8, 0x14 },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
+ 0xff, 0x44, 0x89, 0x32, 0x0e, 0xb5, 0x78, 0xc3 },
+ { 0x00, 0xd0, 0xa0, 0x70, 0x40, 0x90, 0xe0, 0x30,
+ 0x80, 0x50, 0x20, 0xf0, 0xc0, 0x10, 0x60, 0xb0 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xfd, 0xfa, 0x07, 0xf4, 0x09, 0x0e, 0xf3,
+ 0xe8, 0x15, 0x12, 0xef, 0x1c, 0xe1, 0xe6, 0x1b },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
+ 0xe2, 0x59, 0x94, 0x2f, 0x13, 0xa8, 0x65, 0xde },
+ { 0x00, 0xe0, 0xc0, 0x20, 0x80, 0x60, 0x40, 0xa0,
+ 0x00, 0xe0, 0xc0, 0x20, 0x80, 0x60, 0x40, 0xa0 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xfe, 0xfc, 0x02, 0xf8, 0x06, 0x04, 0xfa,
+ 0xf0, 0x0e, 0x0c, 0xf2, 0x08, 0xf6, 0xf4, 0x0a },
+ { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
+ 0xe2, 0x59, 0x94, 0x2f, 0x13, 0xa8, 0x65, 0xde },
+ { 0x00, 0xf0, 0xe0, 0x10, 0xc0, 0x30, 0x20, 0xd0,
+ 0x80, 0x70, 0x60, 0x90, 0x40, 0xb0, 0xa0, 0x50 },
+ { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
+ 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 },
+ { 0x00, 0xff, 0xfe, 0x01, 0xfc, 0x03, 0x02, 0xfd,
+ 0xf8, 0x07, 0x06, 0xf9, 0x04, 0xfb, 0xfa, 0x05 }
+};
+/* END CSTYLED */
+#endif // ENDIANESS
+#endif /* defined(__powerpc__) */
diff --git a/module/zfs/vdev_raidz_math_powerpc_altivec_common.h b/module/zfs/vdev_raidz_math_powerpc_altivec_common.h
new file mode 100644
index 000000000..1e5748952
--- /dev/null
+++ b/module/zfs/vdev_raidz_math_powerpc_altivec_common.h
@@ -0,0 +1,688 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (C) 2019 Romain Dolbeau. All rights reserved.
+ * <[email protected]>
+ */
+
+#include <sys/types.h>
+#include <sys/simd.h>
+
+#define __asm __asm__ __volatile__
+
+#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
+#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
+
+#define VR0_(REG, ...) "%[w"#REG"]"
+#define VR1_(_1, REG, ...) "%[w"#REG"]"
+#define VR2_(_1, _2, REG, ...) "%[w"#REG"]"
+#define VR3_(_1, _2, _3, REG, ...) "%[w"#REG"]"
+#define VR4_(_1, _2, _3, _4, REG, ...) "%[w"#REG"]"
+#define VR5_(_1, _2, _3, _4, _5, REG, ...) "%[w"#REG"]"
+#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "%[w"#REG"]"
+#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "%[w"#REG"]"
+
+/*
+ * Here we need registers not used otherwise.
+ * They will be used in unused ASM for the case
+ * with more registers than required... but GCC
+ * will still need to make sure the constraints
+ * are correct, and duplicate constraints are illegal
+ * ... and we use the "register" number as a name
+ */
+
+#define VR0(r...) VR0_(r)
+#define VR1(r...) VR1_(r)
+#define VR2(r...) VR2_(r, 36)
+#define VR3(r...) VR3_(r, 36, 35)
+#define VR4(r...) VR4_(r, 36, 35, 34, 33)
+#define VR5(r...) VR5_(r, 36, 35, 34, 33, 32)
+#define VR6(r...) VR6_(r, 36, 35, 34, 33, 32, 31)
+#define VR7(r...) VR7_(r, 36, 35, 34, 33, 32, 31, 30)
+
+#define VR(X) "%[w"#X"]"
+
+#define RVR0_(REG, ...) [w##REG] "v" (w##REG)
+#define RVR1_(_1, REG, ...) [w##REG] "v" (w##REG)
+#define RVR2_(_1, _2, REG, ...) [w##REG] "v" (w##REG)
+#define RVR3_(_1, _2, _3, REG, ...) [w##REG] "v" (w##REG)
+#define RVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "v" (w##REG)
+#define RVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "v" (w##REG)
+#define RVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "v" (w##REG)
+#define RVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "v" (w##REG)
+
+#define RVR0(r...) RVR0_(r)
+#define RVR1(r...) RVR1_(r)
+#define RVR2(r...) RVR2_(r, 36)
+#define RVR3(r...) RVR3_(r, 36, 35)
+#define RVR4(r...) RVR4_(r, 36, 35, 34, 33)
+#define RVR5(r...) RVR5_(r, 36, 35, 34, 33, 32)
+#define RVR6(r...) RVR6_(r, 36, 35, 34, 33, 32, 31)
+#define RVR7(r...) RVR7_(r, 36, 35, 34, 33, 32, 31, 30)
+
+#define RVR(X) [w##X] "v" (w##X)
+
+#define WVR0_(REG, ...) [w##REG] "=v" (w##REG)
+#define WVR1_(_1, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR2_(_1, _2, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR3_(_1, _2, _3, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "=v" (w##REG)
+#define WVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "=v" (w##REG)
+
+#define WVR0(r...) WVR0_(r)
+#define WVR1(r...) WVR1_(r)
+#define WVR2(r...) WVR2_(r, 36)
+#define WVR3(r...) WVR3_(r, 36, 35)
+#define WVR4(r...) WVR4_(r, 36, 35, 34, 33)
+#define WVR5(r...) WVR5_(r, 36, 35, 34, 33, 32)
+#define WVR6(r...) WVR6_(r, 36, 35, 34, 33, 32, 31)
+#define WVR7(r...) WVR7_(r, 36, 35, 34, 33, 32, 31, 30)
+
+#define WVR(X) [w##X] "=v" (w##X)
+
+#define UVR0_(REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR1_(_1, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR2_(_1, _2, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR3_(_1, _2, _3, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "+&v" (w##REG)
+#define UVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "+&v" (w##REG)
+
+#define UVR0(r...) UVR0_(r)
+#define UVR1(r...) UVR1_(r)
+#define UVR2(r...) UVR2_(r, 36)
+#define UVR3(r...) UVR3_(r, 36, 35)
+#define UVR4(r...) UVR4_(r, 36, 35, 34, 33)
+#define UVR5(r...) UVR5_(r, 36, 35, 34, 33, 32)
+#define UVR6(r...) UVR6_(r, 36, 35, 34, 33, 32, 31)
+#define UVR7(r...) UVR7_(r, 36, 35, 34, 33, 32, 31, 30)
+
+#define UVR(X) [w##X] "+&v" (w##X)
+
+#define R_01(REG1, REG2, ...) REG1, REG2
+#define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3
+#define R_23(REG...) _R_23(REG, 1, 2, 3)
+
+#define ZFS_ASM_BUG() ASSERT(0)
+
+#define OFFSET(ptr, val) (((unsigned char *)(ptr))+val)
+
+extern const uint8_t gf_clmul_mod_lt[4*256][16];
+
+#define ELEM_SIZE 16
+
+typedef struct v {
+ uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
+} v_t;
+
+#define XOR_ACC(src, r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "lvx 21,0,%[SRC0]\n" \
+ "lvx 20,0,%[SRC1]\n" \
+ "lvx 19,0,%[SRC2]\n" \
+ "lvx 18,0,%[SRC3]\n" \
+ "vxor " VR0(r) "," VR0(r) ",21\n" \
+ "vxor " VR1(r) "," VR1(r) ",20\n" \
+ "vxor " VR2(r) "," VR2(r) ",19\n" \
+ "vxor " VR3(r) "," VR3(r) ",18\n" \
+ "lvx 21,0,%[SRC4]\n" \
+ "lvx 20,0,%[SRC5]\n" \
+ "lvx 19,0,%[SRC6]\n" \
+ "lvx 18,0,%[SRC7]\n" \
+ "vxor " VR4(r) "," VR4(r) ",21\n" \
+ "vxor " VR5(r) "," VR5(r) ",20\n" \
+ "vxor " VR6(r) "," VR6(r) ",19\n" \
+ "vxor " VR7(r) "," VR7(r) ",18\n" \
+ : UVR0(r), UVR1(r), UVR2(r), UVR3(r), \
+ UVR4(r), UVR5(r), UVR6(r), UVR7(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16))), \
+ [SRC2] "r" ((OFFSET(src, 32))), \
+ [SRC3] "r" ((OFFSET(src, 48))), \
+ [SRC4] "r" ((OFFSET(src, 64))), \
+ [SRC5] "r" ((OFFSET(src, 80))), \
+ [SRC6] "r" ((OFFSET(src, 96))), \
+ [SRC7] "r" ((OFFSET(src, 112))) \
+ : "v18", "v19", "v20", "v21"); \
+ break; \
+ case 4: \
+ __asm( \
+ "lvx 21,0,%[SRC0]\n" \
+ "lvx 20,0,%[SRC1]\n" \
+ "lvx 19,0,%[SRC2]\n" \
+ "lvx 18,0,%[SRC3]\n" \
+ "vxor " VR0(r) "," VR0(r) ",21\n" \
+ "vxor " VR1(r) "," VR1(r) ",20\n" \
+ "vxor " VR2(r) "," VR2(r) ",19\n" \
+ "vxor " VR3(r) "," VR3(r) ",18\n" \
+ : UVR0(r), UVR1(r), UVR2(r), UVR3(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16))), \
+ [SRC2] "r" ((OFFSET(src, 32))), \
+ [SRC3] "r" ((OFFSET(src, 48))) \
+ : "v18", "v19", "v20", "v21"); \
+ break; \
+ case 2: \
+ __asm( \
+ "lvx 21,0,%[SRC0]\n" \
+ "lvx 20,0,%[SRC1]\n" \
+ "vxor " VR0(r) "," VR0(r) ",21\n" \
+ "vxor " VR1(r) "," VR1(r) ",20\n" \
+ : UVR0(r), UVR1(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16))) \
+ : "v20", "v21"); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define XOR(r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "vxor " VR4(r) "," VR4(r) "," VR0(r) "\n" \
+ "vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
+ "vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
+ "vxor " VR7(r) "," VR7(r) "," VR3(r) "\n" \
+ : UVR4(r), UVR5(r), UVR6(r), UVR7(r) \
+ : RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
+ break; \
+ case 4: \
+ __asm( \
+ "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
+ "vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
+ : UVR2(r), UVR3(r) \
+ : RVR0(r), RVR1(r)); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define ZERO(r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
+ "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
+ "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
+ "vxor " VR3(r) "," VR3(r) "," VR3(r) "\n" \
+ "vxor " VR4(r) "," VR4(r) "," VR4(r) "\n" \
+ "vxor " VR5(r) "," VR5(r) "," VR5(r) "\n" \
+ "vxor " VR6(r) "," VR6(r) "," VR6(r) "\n" \
+ "vxor " VR7(r) "," VR7(r) "," VR7(r) "\n" \
+ : WVR0(r), WVR1(r), WVR2(r), WVR3(r), \
+ WVR4(r), WVR5(r), WVR6(r), WVR7(r)); \
+ break; \
+ case 4: \
+ __asm( \
+ "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
+ "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
+ "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
+ "vxor " VR3(r) "," VR3(r) "," VR3(r) "\n" \
+ : WVR0(r), WVR1(r), WVR2(r), WVR3(r)); \
+ break; \
+ case 2: \
+ __asm( \
+ "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
+ "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
+ : WVR0(r), WVR1(r)); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define COPY(r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "vor " VR4(r) "," VR0(r) "," VR0(r) "\n" \
+ "vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
+ "vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \
+ "vor " VR7(r) "," VR3(r) "," VR3(r) "\n" \
+ : WVR4(r), WVR5(r), WVR6(r), WVR7(r) \
+ : RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
+ break; \
+ case 4: \
+ __asm( \
+ "vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \
+ "vor " VR3(r) "," VR1(r) "," VR1(r) "\n" \
+ : WVR2(r), WVR3(r) \
+ : RVR0(r), RVR1(r)); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define LOAD(src, r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "lvx " VR0(r) " ,0,%[SRC0]\n" \
+ "lvx " VR1(r) " ,0,%[SRC1]\n" \
+ "lvx " VR2(r) " ,0,%[SRC2]\n" \
+ "lvx " VR3(r) " ,0,%[SRC3]\n" \
+ "lvx " VR4(r) " ,0,%[SRC4]\n" \
+ "lvx " VR5(r) " ,0,%[SRC5]\n" \
+ "lvx " VR6(r) " ,0,%[SRC6]\n" \
+ "lvx " VR7(r) " ,0,%[SRC7]\n" \
+ : WVR0(r), WVR1(r), WVR2(r), WVR3(r), \
+ WVR4(r), WVR5(r), WVR6(r), WVR7(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16))), \
+ [SRC2] "r" ((OFFSET(src, 32))), \
+ [SRC3] "r" ((OFFSET(src, 48))), \
+ [SRC4] "r" ((OFFSET(src, 64))), \
+ [SRC5] "r" ((OFFSET(src, 80))), \
+ [SRC6] "r" ((OFFSET(src, 96))), \
+ [SRC7] "r" ((OFFSET(src, 112)))); \
+ break; \
+ case 4: \
+ __asm( \
+ "lvx " VR0(r) " ,0,%[SRC0]\n" \
+ "lvx " VR1(r) " ,0,%[SRC1]\n" \
+ "lvx " VR2(r) " ,0,%[SRC2]\n" \
+ "lvx " VR3(r) " ,0,%[SRC3]\n" \
+ : WVR0(r), WVR1(r), WVR2(r), WVR3(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16))), \
+ [SRC2] "r" ((OFFSET(src, 32))), \
+ [SRC3] "r" ((OFFSET(src, 48)))); \
+ break; \
+ case 2: \
+ __asm( \
+ "lvx " VR0(r) " ,0,%[SRC0]\n" \
+ "lvx " VR1(r) " ,0,%[SRC1]\n" \
+ : WVR0(r), WVR1(r) \
+ : [SRC0] "r" ((OFFSET(src, 0))), \
+ [SRC1] "r" ((OFFSET(src, 16)))); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define STORE(dst, r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 8: \
+ __asm( \
+ "stvx " VR0(r) " ,0,%[DST0]\n" \
+ "stvx " VR1(r) " ,0,%[DST1]\n" \
+ "stvx " VR2(r) " ,0,%[DST2]\n" \
+ "stvx " VR3(r) " ,0,%[DST3]\n" \
+ "stvx " VR4(r) " ,0,%[DST4]\n" \
+ "stvx " VR5(r) " ,0,%[DST5]\n" \
+ "stvx " VR6(r) " ,0,%[DST6]\n" \
+ "stvx " VR7(r) " ,0,%[DST7]\n" \
+ : : [DST0] "r" ((OFFSET(dst, 0))), \
+ [DST1] "r" ((OFFSET(dst, 16))), \
+ [DST2] "r" ((OFFSET(dst, 32))), \
+ [DST3] "r" ((OFFSET(dst, 48))), \
+ [DST4] "r" ((OFFSET(dst, 64))), \
+ [DST5] "r" ((OFFSET(dst, 80))), \
+ [DST6] "r" ((OFFSET(dst, 96))), \
+ [DST7] "r" ((OFFSET(dst, 112))), \
+ RVR0(r), RVR1(r), RVR2(r), RVR3(r), \
+ RVR4(r), RVR5(r), RVR6(r), RVR7(r) \
+ : "memory"); \
+ break; \
+ case 4: \
+ __asm( \
+ "stvx " VR0(r) " ,0,%[DST0]\n" \
+ "stvx " VR1(r) " ,0,%[DST1]\n" \
+ "stvx " VR2(r) " ,0,%[DST2]\n" \
+ "stvx " VR3(r) " ,0,%[DST3]\n" \
+ : : [DST0] "r" ((OFFSET(dst, 0))), \
+ [DST1] "r" ((OFFSET(dst, 16))), \
+ [DST2] "r" ((OFFSET(dst, 32))), \
+ [DST3] "r" ((OFFSET(dst, 48))), \
+ RVR0(r), RVR1(r), RVR2(r), RVR3(r) \
+ : "memory"); \
+ break; \
+ case 2: \
+ __asm( \
+ "stvx " VR0(r) " ,0,%[DST0]\n" \
+ "stvx " VR1(r) " ,0,%[DST1]\n" \
+ : : [DST0] "r" ((OFFSET(dst, 0))), \
+ [DST1] "r" ((OFFSET(dst, 16))), \
+ RVR0(r), RVR1(r) : "memory"); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+/*
+ * Unfortunately cannot use the macro, because GCC
+ * will try to use the macro name and not value
+ * later on...
+ * Kept as a reference to what a numbered variable is
+ */
+#define _00 "17"
+#define _1d "16"
+#define _temp0 "19"
+#define _temp1 "18"
+
+#define MUL2_SETUP() \
+{ \
+ __asm( \
+ "vspltisb " VR(16) ",14\n" \
+ "vspltisb " VR(17) ",15\n" \
+ "vaddubm " VR(16) "," VR(17) "," VR(16) "\n" \
+ "vxor " VR(17) "," VR(17) "," VR(17) "\n" \
+ : WVR(16), WVR(17)); \
+}
+
+#define MUL2(r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 4: \
+ __asm( \
+ "vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
+ "vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
+ "vcmpgtsb 21," VR(17) "," VR2(r) "\n" \
+ "vcmpgtsb 20," VR(17) "," VR3(r) "\n" \
+ "vand 19,19," VR(16) "\n" \
+ "vand 18,18," VR(16) "\n" \
+ "vand 21,21," VR(16) "\n" \
+ "vand 20,20," VR(16) "\n" \
+ "vaddubm " VR0(r) "," VR0(r) "," VR0(r) "\n" \
+ "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \
+ "vaddubm " VR2(r) "," VR2(r) "," VR2(r) "\n" \
+ "vaddubm " VR3(r) "," VR3(r) "," VR3(r) "\n" \
+ "vxor " VR0(r) ",19," VR0(r) "\n" \
+ "vxor " VR1(r) ",18," VR1(r) "\n" \
+ "vxor " VR2(r) ",21," VR2(r) "\n" \
+ "vxor " VR3(r) ",20," VR3(r) "\n" \
+ : UVR0(r), UVR1(r), UVR2(r), UVR3(r) \
+ : RVR(17), RVR(16) \
+ : "v18", "v19", "v20", "v21"); \
+ break; \
+ case 2: \
+ __asm( \
+ "vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
+ "vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
+ "vand 19,19," VR(16) "\n" \
+ "vand 18,18," VR(16) "\n" \
+ "vaddubm " VR0(r) "," VR0(r) "," VR0(r) "\n" \
+ "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \
+ "vxor " VR0(r) ",19," VR0(r) "\n" \
+ "vxor " VR1(r) ",18," VR1(r) "\n" \
+ : UVR0(r), UVR1(r) \
+ : RVR(17), RVR(16) \
+ : "v18", "v19"); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define MUL4(r...) \
+{ \
+ MUL2(r); \
+ MUL2(r); \
+}
+
+/*
+ * Unfortunately cannot use the macro, because GCC
+ * will try to use the macro name and not value
+ * later on...
+ * Kept as a reference to what a register is
+ * (here we're using actual registers for the
+ * clobbered ones)
+ */
+#define _0f "15"
+#define _a_save "14"
+#define _b_save "13"
+#define _lt_mod_a "12"
+#define _lt_clmul_a "11"
+#define _lt_mod_b "10"
+#define _lt_clmul_b "15"
+
+#define _MULx2(c, r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 2: \
+ __asm( \
+ /* lts for upper part */ \
+ "vspltisb 15,15\n" \
+ "lvx 10,0,%[lt0]\n" \
+ "lvx 11,0,%[lt1]\n" \
+ /* upper part */ \
+ "vand 14," VR0(r) ",15\n" \
+ "vand 13," VR1(r) ",15\n" \
+ "vspltisb 15,4\n" \
+ "vsrab " VR0(r) "," VR0(r) ",15\n" \
+ "vsrab " VR1(r) "," VR1(r) ",15\n" \
+ \
+ "vperm 12,10,10," VR0(r) "\n" \
+ "vperm 10,10,10," VR1(r) "\n" \
+ "vperm 15,11,11," VR0(r) "\n" \
+ "vperm 11,11,11," VR1(r) "\n" \
+ \
+ "vxor " VR0(r) ",15,12\n" \
+ "vxor " VR1(r) ",11,10\n" \
+ /* lts for lower part */ \
+ "lvx 10,0,%[lt2]\n" \
+ "lvx 15,0,%[lt3]\n" \
+ /* lower part */ \
+ "vperm 12,10,10,14\n" \
+ "vperm 10,10,10,13\n" \
+ "vperm 11,15,15,14\n" \
+ "vperm 15,15,15,13\n" \
+ \
+ "vxor " VR0(r) "," VR0(r) ",12\n" \
+ "vxor " VR1(r) "," VR1(r) ",10\n" \
+ "vxor " VR0(r) "," VR0(r) ",11\n" \
+ "vxor " VR1(r) "," VR1(r) ",15\n" \
+ : UVR0(r), UVR1(r) \
+ : [lt0] "r" (&(gf_clmul_mod_lt[4*(c)+0][0])), \
+ [lt1] "r" (&(gf_clmul_mod_lt[4*(c)+1][0])), \
+ [lt2] "r" (&(gf_clmul_mod_lt[4*(c)+2][0])), \
+ [lt3] "r" (&(gf_clmul_mod_lt[4*(c)+3][0])) \
+ : "v10", "v11", "v12", "v13", "v14", "v15"); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define MUL(c, r...) \
+{ \
+ switch (REG_CNT(r)) { \
+ case 4: \
+ _MULx2(c, R_23(r)); \
+ _MULx2(c, R_01(r)); \
+ break; \
+ case 2: \
+ _MULx2(c, R_01(r)); \
+ break; \
+ default: \
+ ZFS_ASM_BUG(); \
+ } \
+}
+
+#define raidz_math_begin() kfpu_begin()
+#define raidz_math_end() kfpu_end()
+
+/* Overkill... */
+#if 0 // defined(_KERNEL)
+#define GEN_X_DEFINE_0_3() \
+register unsigned char w0 asm("0") __attribute__((vector_size(16))); \
+register unsigned char w1 asm("1") __attribute__((vector_size(16))); \
+register unsigned char w2 asm("2") __attribute__((vector_size(16))); \
+register unsigned char w3 asm("3") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_4_5() \
+register unsigned char w4 asm("4") __attribute__((vector_size(16))); \
+register unsigned char w5 asm("5") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_6_7() \
+register unsigned char w6 asm("6") __attribute__((vector_size(16))); \
+register unsigned char w7 asm("7") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_8_9() \
+register unsigned char w8 asm("8") __attribute__((vector_size(16))); \
+register unsigned char w9 asm("9") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_10_11() \
+register unsigned char w10 asm("10") __attribute__((vector_size(16))); \
+register unsigned char w11 asm("11") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_12_15() \
+register unsigned char w12 asm("12") __attribute__((vector_size(16))); \
+register unsigned char w13 asm("13") __attribute__((vector_size(16))); \
+register unsigned char w14 asm("14") __attribute__((vector_size(16))); \
+register unsigned char w15 asm("15") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_16() \
+register unsigned char w16 asm("16") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_17() \
+register unsigned char w17 asm("17") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_18_21() \
+register unsigned char w18 asm("18") __attribute__((vector_size(16))); \
+register unsigned char w19 asm("19") __attribute__((vector_size(16))); \
+register unsigned char w20 asm("20") __attribute__((vector_size(16))); \
+register unsigned char w21 asm("21") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_22_23() \
+register unsigned char w22 asm("22") __attribute__((vector_size(16))); \
+register unsigned char w23 asm("23") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_24_27() \
+register unsigned char w24 asm("24") __attribute__((vector_size(16))); \
+register unsigned char w25 asm("25") __attribute__((vector_size(16))); \
+register unsigned char w26 asm("26") __attribute__((vector_size(16))); \
+register unsigned char w27 asm("27") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_28_30() \
+register unsigned char w28 asm("28") __attribute__((vector_size(16))); \
+register unsigned char w29 asm("29") __attribute__((vector_size(16))); \
+register unsigned char w30 asm("30") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_31() \
+register unsigned char w31 asm("31") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_32() \
+register unsigned char w32 asm("31") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_33_36() \
+register unsigned char w33 asm("31") __attribute__((vector_size(16))); \
+register unsigned char w34 asm("31") __attribute__((vector_size(16))); \
+register unsigned char w35 asm("31") __attribute__((vector_size(16))); \
+register unsigned char w36 asm("31") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_37_38() \
+register unsigned char w37 asm("31") __attribute__((vector_size(16))); \
+register unsigned char w38 asm("31") __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_ALL() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_8_9() \
+ GEN_X_DEFINE_10_11() \
+ GEN_X_DEFINE_12_15() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_18_21() \
+ GEN_X_DEFINE_22_23() \
+ GEN_X_DEFINE_24_27() \
+ GEN_X_DEFINE_28_30() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36() \
+ GEN_X_DEFINE_37_38()
+#else
+#define GEN_X_DEFINE_0_3() \
+ unsigned char w0 __attribute__((vector_size(16))); \
+ unsigned char w1 __attribute__((vector_size(16))); \
+ unsigned char w2 __attribute__((vector_size(16))); \
+ unsigned char w3 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_4_5() \
+ unsigned char w4 __attribute__((vector_size(16))); \
+ unsigned char w5 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_6_7() \
+ unsigned char w6 __attribute__((vector_size(16))); \
+ unsigned char w7 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_8_9() \
+ unsigned char w8 __attribute__((vector_size(16))); \
+ unsigned char w9 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_10_11() \
+ unsigned char w10 __attribute__((vector_size(16))); \
+ unsigned char w11 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_12_15() \
+ unsigned char w12 __attribute__((vector_size(16))); \
+ unsigned char w13 __attribute__((vector_size(16))); \
+ unsigned char w14 __attribute__((vector_size(16))); \
+ unsigned char w15 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_16() \
+ unsigned char w16 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_17() \
+ unsigned char w17 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_18_21() \
+ unsigned char w18 __attribute__((vector_size(16))); \
+ unsigned char w19 __attribute__((vector_size(16))); \
+ unsigned char w20 __attribute__((vector_size(16))); \
+ unsigned char w21 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_22_23() \
+ unsigned char w22 __attribute__((vector_size(16))); \
+ unsigned char w23 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_24_27() \
+ unsigned char w24 __attribute__((vector_size(16))); \
+ unsigned char w25 __attribute__((vector_size(16))); \
+ unsigned char w26 __attribute__((vector_size(16))); \
+ unsigned char w27 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_28_30() \
+ unsigned char w28 __attribute__((vector_size(16))); \
+ unsigned char w29 __attribute__((vector_size(16))); \
+ unsigned char w30 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_31() \
+ unsigned char w31 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_32() \
+ unsigned char w32 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_33_36() \
+ unsigned char w33 __attribute__((vector_size(16))); \
+ unsigned char w34 __attribute__((vector_size(16))); \
+ unsigned char w35 __attribute__((vector_size(16))); \
+ unsigned char w36 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_37_38() \
+ unsigned char w37 __attribute__((vector_size(16))); \
+ unsigned char w38 __attribute__((vector_size(16)));
+#define GEN_X_DEFINE_ALL() \
+ GEN_X_DEFINE_0_3() \
+ GEN_X_DEFINE_4_5() \
+ GEN_X_DEFINE_6_7() \
+ GEN_X_DEFINE_8_9() \
+ GEN_X_DEFINE_10_11() \
+ GEN_X_DEFINE_12_15() \
+ GEN_X_DEFINE_16() \
+ GEN_X_DEFINE_17() \
+ GEN_X_DEFINE_18_21() \
+ GEN_X_DEFINE_22_23() \
+ GEN_X_DEFINE_24_27() \
+ GEN_X_DEFINE_28_30() \
+ GEN_X_DEFINE_31() \
+ GEN_X_DEFINE_32() \
+ GEN_X_DEFINE_33_36() \
+ GEN_X_DEFINE_37_38()
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 09:08:35 +0000