1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
|
/*
* Copyright © 2014-2017 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
/**
* @file v3d_simulator_hw.c
*
* Implements the actual HW interaction betweeh the GL driver's VC5 simulator and the simulator.
*
* The register headers between V3D versions will have conflicting defines, so
* all register interactions appear in this file and are compiled per V3D version
* we support.
*/
#ifdef USE_V3D_SIMULATOR
#include "v3d_screen.h"
#include "v3d_context.h"
#include "v3d_simulator_wrapper.h"
#define HW_REGISTER_RO(x) (x)
#define HW_REGISTER_RW(x) (x)
#if V3D_VERSION >= 41
#include "libs/core/v3d/registers/4.1.34.0/v3d.h"
#else
#include "libs/core/v3d/registers/3.3.0.0/v3d.h"
#endif
#define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
#define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
static void
v3d_flush_l3(struct v3d_hw *v3d)
{
if (!v3d_hw_has_gca(v3d))
return;
#if V3D_VERSION < 40
uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
#endif
}
/* Invalidates the L2 cache. This is a read-only cache. */
static void
v3d_flush_l2(struct v3d_hw *v3d)
{
V3D_WRITE(V3D_CTL_0_L2CACTL,
V3D_CTL_0_L2CACTL_L2CCLR_SET |
V3D_CTL_0_L2CACTL_L2CENA_SET);
}
/* Invalidates texture L2 cachelines */
static void
v3d_flush_l2t(struct v3d_hw *v3d)
{
V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
V3D_WRITE(V3D_CTL_0_L2TCACTL,
V3D_CTL_0_L2TCACTL_L2TFLS_SET |
(0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
}
/* Invalidates the slice caches. These are read-only caches. */
static void
v3d_flush_slices(struct v3d_hw *v3d)
{
V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
}
static void
v3d_flush_caches(struct v3d_hw *v3d)
{
v3d_flush_l3(v3d);
v3d_flush_l2(v3d);
v3d_flush_l2t(v3d);
v3d_flush_slices(v3d);
}
int
v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
struct drm_v3d_get_param *args)
{
static const uint32_t reg_map[] = {
[DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
[DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
[DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
[DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
[DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
[DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
[DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
};
if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
args->value = V3D_READ(reg_map[args->param]);
return 0;
}
fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
(long long)args->value);
abort();
}
void
v3dX(simulator_init_regs)(struct v3d_hw *v3d)
{
#if V3D_VERSION == 33
/* Set OVRTMUOUT to match kernel behavior.
*
* This means that the texture sampler uniform configuration's tmu
* output type field is used, instead of using the hardware default
* behavior based on the texture type. If you want the default
* behavior, you can still put "2" in the indirect texture state's
* output_type field.
*/
V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
#endif
}
void
v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_v3d_submit_cl *submit,
uint32_t gmp_ofs)
{
/* Completely reset the GMP. */
V3D_WRITE(V3D_GMP_0_CFG,
V3D_GMP_0_CFG_PROTENABLE_SET);
V3D_WRITE(V3D_GMP_0_TABLE_ADDR, gmp_ofs);
V3D_WRITE(V3D_GMP_0_CLEAR_LOAD, ~0);
while (V3D_READ(V3D_GMP_0_STATUS) &
V3D_GMP_0_STATUS_CFG_BUSY_SET) {
;
}
v3d_flush_caches(v3d);
if (submit->qma) {
V3D_WRITE(V3D_CLE_0_CT0QMA, submit->qma);
V3D_WRITE(V3D_CLE_0_CT0QMS, submit->qms);
}
#if V3D_VERSION >= 41
if (submit->qts) {
V3D_WRITE(V3D_CLE_0_CT0QTS,
V3D_CLE_0_CT0QTS_CTQTSEN_SET |
submit->qts);
}
#endif
V3D_WRITE(V3D_CLE_0_CT0QBA, submit->bcl_start);
V3D_WRITE(V3D_CLE_0_CT0QEA, submit->bcl_end);
/* Wait for bin to complete before firing render, as it seems the
* simulator doesn't implement the semaphores.
*/
while (V3D_READ(V3D_CLE_0_CT0CA) !=
V3D_READ(V3D_CLE_0_CT0EA)) {
v3d_hw_tick(v3d);
}
V3D_WRITE(V3D_CLE_0_CT1QBA, submit->rcl_start);
V3D_WRITE(V3D_CLE_0_CT1QEA, submit->rcl_end);
while (V3D_READ(V3D_CLE_0_CT1CA) !=
V3D_READ(V3D_CLE_0_CT1EA) ||
V3D_READ(V3D_CLE_1_CT1CA) !=
V3D_READ(V3D_CLE_1_CT1EA)) {
v3d_hw_tick(v3d);
}
}
#endif /* USE_V3D_SIMULATOR */
|
