blob: 5ee77fafe2b590854aa8c9a9bf152c4d4a971af3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
//===-- AMDGPULowerShaderInstructions.h - TODO: Add brief description -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#ifndef AMDGPU_LOWER_SHADER_INSTRUCTIONS
#define AMDGPU_LOWER_SHADER_INSTRUCTIONS
namespace llvm {
class MachineFunction;
class MachineRegisterInfo;
class TargetInstrInfo;
class AMDGPULowerShaderInstructionsPass {
protected:
MachineRegisterInfo * MRI;
/**
* @param physReg The physical register that will be preloaded.
* @param virtReg The virtual register that currently holds the
* preloaded value.
*/
void preloadRegister(MachineFunction * MF, const TargetInstrInfo * TII,
unsigned physReg, unsigned virtReg) const;
};
} // end namespace llvm
#endif // AMDGPU_LOWER_SHADER_INSTRUCTIONS
|
