1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
|
/*
* Copyright (c) 2017 Lima Project
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "util/bitscan.h"
#include "util/ralloc.h"
#include "ppir.h"
static bool ppir_lower_const(ppir_block *block, ppir_node *node)
{
if (ppir_node_is_root(node)) {
ppir_node_delete(node);
return true;
}
ppir_node *move = NULL;
ppir_dest *dest = ppir_node_get_dest(node);
/* const (register) can only be used in alu node, create a move
* node for other types of node */
ppir_node_foreach_succ_safe(node, dep) {
ppir_node *succ = dep->succ;
if (succ->type != ppir_node_type_alu) {
if (!move) {
move = ppir_node_create(block, ppir_op_mov, -1, 0);
if (unlikely(!move))
return false;
ppir_debug("lower const create move %d for %d\n",
move->index, node->index);
ppir_alu_node *alu = ppir_node_to_alu(move);
alu->dest = *dest;
alu->num_src = 1;
ppir_node_target_assign(alu->src, dest);
for (int i = 0; i < 4; i++)
alu->src->swizzle[i] = i;
}
ppir_node_replace_pred(dep, move);
ppir_node_replace_child(succ, node, move);
}
}
if (move) {
ppir_node_add_dep(move, node);
list_addtail(&move->list, &node->list);
}
return true;
}
static bool ppir_lower_swap_args(ppir_block *block, ppir_node *node)
{
/* swapped op must be the next op */
node->op++;
assert(node->type == ppir_node_type_alu);
ppir_alu_node *alu = ppir_node_to_alu(node);
assert(alu->num_src == 2);
ppir_src tmp = alu->src[0];
alu->src[0] = alu->src[1];
alu->src[1] = tmp;
return true;
}
static bool ppir_lower_load(ppir_block *block, ppir_node *node)
{
ppir_node *move = ppir_node_create(block, ppir_op_mov, -1 , 0);
if (unlikely(!move))
return false;
ppir_alu_node *alu = ppir_node_to_alu(move);
ppir_dest *dest = ppir_node_get_dest(node);
alu->dest = *dest;
ppir_node_replace_all_succ(move, node);
dest->type = ppir_target_pipeline;
dest->pipeline = ppir_pipeline_reg_uniform;
alu->num_src = 1;
ppir_node_target_assign(&alu->src[0], dest);
for (int i = 0; i < 4; i++)
alu->src->swizzle[i] = i;
ppir_node_add_dep(move, node);
list_addtail(&move->list, &node->list);
return true;
}
static bool ppir_lower_texture(ppir_block *block, ppir_node *node)
{
ppir_load_texture_node *load_tex = ppir_node_to_load_texture(node);
/* Create load_coords node */
ppir_load_node *load = ppir_node_create(block, ppir_op_load_coords, -1, 0);
if (!load)
return false;
list_addtail(&load->node.list, &node->list);
ppir_debug("%s create load_coords node %d for %d\n",
__FUNCTION__, load->node.index, node->index);
load->dest.type = ppir_target_pipeline;
load->dest.pipeline = ppir_pipeline_reg_discard;
load->src = load_tex->src_coords;
ppir_node_foreach_pred_safe(node, dep) {
ppir_node *pred = dep->pred;
ppir_node_remove_dep(dep);
ppir_node_add_dep(&load->node, pred);
}
ppir_node_add_dep(node, &load->node);
/* Create move node */
ppir_node *move = ppir_node_create(block, ppir_op_mov, -1 , 0);
if (unlikely(!move))
return false;
ppir_alu_node *alu = ppir_node_to_alu(move);
ppir_dest *dest = ppir_node_get_dest(node);
alu->dest = *dest;
ppir_node_replace_all_succ(move, node);
dest->type = ppir_target_pipeline;
dest->pipeline = ppir_pipeline_reg_sampler;
alu->num_src = 1;
ppir_node_target_assign(&alu->src[0], dest);
for (int i = 0; i < 4; i++)
alu->src->swizzle[i] = i;
ppir_node_add_dep(move, node);
list_addtail(&move->list, &node->list);
return true;
}
/* insert a move as the select condition to make sure it can
* be inserted to select instr float mul slot
*/
static bool ppir_lower_select(ppir_block *block, ppir_node *node)
{
ppir_alu_node *alu = ppir_node_to_alu(node);
ppir_node *move = ppir_node_create(block, ppir_op_sel_cond, -1, 0);
if (!move)
return false;
list_addtail(&move->list, &node->list);
ppir_alu_node *move_alu = ppir_node_to_alu(move);
ppir_src *move_src = move_alu->src, *src = alu->src;
move_src->type = src->type;
move_src->ssa = src->ssa;
move_src->swizzle[0] = src->swizzle[0];
move_alu->num_src = 1;
ppir_dest *move_dest = &move_alu->dest;
move_dest->type = ppir_target_pipeline;
move_dest->pipeline = ppir_pipeline_reg_fmul;
move_dest->write_mask = 1;
ppir_node_foreach_pred(node, dep) {
ppir_node *pred = dep->pred;
ppir_dest *dest = ppir_node_get_dest(pred);
if (ppir_node_target_equal(alu->src, dest)) {
ppir_node_replace_pred(dep, move);
ppir_node_add_dep(move, pred);
}
}
/* move must be the first pred of select node which make sure
* the float mul slot is free when node to instr
*/
assert(ppir_node_first_pred(node) == move);
src->swizzle[0] = 0;
ppir_node_target_assign(alu->src, move_dest);
return true;
}
static bool ppir_lower_trunc(ppir_block *block, ppir_node *node)
{
/* Turn it into a mov with a round to integer output modifier */
ppir_alu_node *alu = ppir_node_to_alu(node);
ppir_dest *move_dest = &alu->dest;
move_dest->modifier = ppir_outmod_round;
node->op = ppir_op_mov;
return true;
}
static bool ppir_lower_abs(ppir_block *block, ppir_node *node)
{
/* Turn it into a mov and set the absolute modifier */
ppir_alu_node *alu = ppir_node_to_alu(node);
assert(alu->num_src == 1);
alu->src[0].absolute = true;
alu->src[0].negate = false;
node->op = ppir_op_mov;
return true;
}
static bool ppir_lower_neg(ppir_block *block, ppir_node *node)
{
/* Turn it into a mov and set the negate modifier */
ppir_alu_node *alu = ppir_node_to_alu(node);
assert(alu->num_src == 1);
alu->src[0].negate = !alu->src[0].negate;
node->op = ppir_op_mov;
return true;
}
static bool ppir_lower_sat(ppir_block *block, ppir_node *node)
{
/* Turn it into a mov with the saturate output modifier */
ppir_alu_node *alu = ppir_node_to_alu(node);
assert(alu->num_src == 1);
ppir_dest *move_dest = &alu->dest;
move_dest->modifier = ppir_outmod_clamp_fraction;
node->op = ppir_op_mov;
return true;
}
static bool ppir_lower_branch(ppir_block *block, ppir_node *node)
{
ppir_branch_node *branch = ppir_node_to_branch(node);
ppir_const_node *zero = ppir_node_create(block, ppir_op_const, -1, 0);
if (!zero)
return false;
list_addtail(&zero->node.list, &node->list);
zero->constant.value[0].f = 0;
zero->constant.num = 1;
zero->dest.type = ppir_target_ssa;
zero->dest.ssa.num_components = 1;
zero->dest.ssa.live_in = INT_MAX;
zero->dest.ssa.live_out = 0;
zero->dest.write_mask = 0x01;
/* For now we're just comparing branch condition with 0,
* in future we should look whether it's possible to move
* comparision node into branch itself and use current
* way as a fallback for complex conditions.
*/
branch->src[1].type = ppir_target_ssa;
branch->src[1].ssa = &zero->dest.ssa;
branch->cond_gt = true;
branch->cond_lt = true;
ppir_node_add_dep(&branch->node, &zero->node);
return true;
}
static bool (*ppir_lower_funcs[ppir_op_num])(ppir_block *, ppir_node *) = {
[ppir_op_abs] = ppir_lower_abs,
[ppir_op_neg] = ppir_lower_neg,
[ppir_op_const] = ppir_lower_const,
[ppir_op_lt] = ppir_lower_swap_args,
[ppir_op_le] = ppir_lower_swap_args,
[ppir_op_load_texture] = ppir_lower_texture,
[ppir_op_select] = ppir_lower_select,
[ppir_op_trunc] = ppir_lower_trunc,
[ppir_op_sat] = ppir_lower_sat,
[ppir_op_branch] = ppir_lower_branch,
[ppir_op_load_uniform] = ppir_lower_load,
[ppir_op_load_temp] = ppir_lower_load,
};
bool ppir_lower_prog(ppir_compiler *comp)
{
list_for_each_entry(ppir_block, block, &comp->block_list, list) {
list_for_each_entry_safe(ppir_node, node, &block->node_list, list) {
if (ppir_lower_funcs[node->op] &&
!ppir_lower_funcs[node->op](block, node))
return false;
}
}
ppir_node_print_prog(comp);
return true;
}
|