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* freedreno/ir3/sched: fixup new instr's blockRob Clark2015-07-101-0/+4
* freedreno/ir3/ra: fix failed assert for a0/p0Rob Clark2015-07-101-0/+5
* freedreno/ir3: shader-db tracesRob Clark2015-07-107-8/+67
* freedreno: fix crash in fd_invalidate_resource()Rob Clark2015-07-101-2/+2
* vc4: unref old fenceRob Clark2015-07-101-0/+2
* ilo: unref old fenceRob Clark2015-07-101-0/+2
* freedreno: unref old fenceRob Clark2015-07-101-1/+3
* gallium: clarify reference counting for fenceRob Clark2015-07-101-1/+7
* xa: don't leak fencesRob Clark2015-07-103-3/+7
* i965/vs: Get rid of brw_vs_compile completely.Kenneth Graunke2015-07-093-40/+31
* i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.Kenneth Graunke2015-07-094-15/+15
* i965/vec4: Move c->last_scratch into vec4_visitor.Kenneth Graunke2015-07-098-22/+15
* i965/vec4: Move total_scratch calculation into the visitor.Kenneth Graunke2015-07-093-10/+7
* i965/vec4: Move perf_debug about register spilling into the visitor.Kenneth Graunke2015-07-093-11/+13
* i965/vec4: Plumb log_data through so the backend_shader field gets set.Kenneth Graunke2015-07-098-8/+18
* i965: Switch on shader stage in nir_setup_outputs().Kenneth Graunke2015-07-091-26/+33
* tgsi: whitespace fixes in tgsi_parse.cBrian Paul2015-07-091-13/+13
* gallium: fix comment typo in p_shader_tokens.hBrian Paul2015-07-091-1/+1
* gallium/docs: s/treaded/treated/ typo in tgsi.rstBrian Paul2015-07-091-1/+1
* util: Don't link to SHA1 library if shader-cache is disabled.Matt Turner2015-07-091-1/+1
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-092-1/+3
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-092-2/+29
* st/vdpau: fix mixer size checksChristian König2015-07-091-11/+11
* vl: cleanup video buffer private when the decoder is destroyedChristian König2015-07-092-0/+28
* nv50: avoid segfault with enabled but unbound vertex attribSamuel Pitoiset2015-07-081-0/+5
* nvc0: fix wrong use of BLIT_SRC_Y_INT for 2D texture copySamuel Pitoiset2015-07-081-1/+1
* nir: Fix comment above nir_convert_from_ssa() prototype.Kenneth Graunke2015-07-081-3/+3
* egl/dri2: load libglapi.0.dylib on osxJulien Isorce2015-07-081-0/+2
* android: freedreno: add missing components to the buildVarad Gautam2015-07-081-1/+4
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-086-37/+64
* loader: Look for any version of currently linked libudev.soChris Wilson2015-07-081-18/+28
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-083-5/+25
* nvc0: turn sample counts off during blitIlia Mirkin2015-07-071-0/+7
* mesa: use implementation specified MAX_VERTEX_ATTRIBS rather than hardcoded v...Timothy Arceri2015-07-081-6/+2
* i965/vs: Fix matNxM vertex attributes where M != 4.Kenneth Graunke2015-07-071-4/+11
* st/dri: don't set PIPE_BIND_SCANOUT for MSAA surfacesMarek Olšák2015-07-071-1/+1
* gallium/hud: display percentages with % suffixBrian Paul2015-07-071-0/+3
* gallium/hud: add PIPE_DRIVER_QUERY_TYPE_MICROSECONDS for HUDBrian Paul2015-07-072-10/+26
* gallium/hud: replace byte units flag with pipe_driver_query_typeBrian Paul2015-07-073-16/+18
* gallium/os: minor whitespace fixes in os_time.hBrian Paul2015-07-071-5/+6
* i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.Francisco Jerez2015-07-071-7/+1
* i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.Francisco Jerez2015-07-071-1/+1
* i965/gen4-5: Set ENDIF dst and src0 fields to the null register.Francisco Jerez2015-07-071-2/+2
* radeonsi: Use param export count from si_llvm_export_vs in si_shader_vsMichel Dänzer2015-07-073-22/+6
* mesa: Convert some asserts into STATIC_ASSERT.Matt Turner2015-07-061-7/+6
* gallivm: fix lp_build_compare_extRoland Scheidegger2015-07-062-1/+4
* mesa: Add a MUST_CHECK macro for __attribute__((warn_unused_result)).Kenneth Graunke2015-07-061-0/+6
* glsl: Make sure not to dereference NULLNeil Roberts2015-07-061-1/+1
* glsl: Add missing check for whether an expression is an add operationNeil Roberts2015-07-061-1/+1
* i965: Reserve more batch space to accomodate Gen6 perfmonitors.Kenneth Graunke2015-07-061-2/+2
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