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* radeonsi: add AMD_DEBUG=nodmacopyimage for debuggingMarek Olšák2020-01-063-1/+4
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-By: Timur Kristóf <[email protected]>
* radeonsi: add AMD_DEBUG=nodmaclear for debuggingMarek Olšák2020-01-063-1/+4
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-By: Timur Kristóf <[email protected]>
* radeonsi: remove broken and unused SI SDMA image copy codeMarek Olšák2020-01-061-181/+2
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-By: Timur Kristóf <[email protected]>
* radeonsi: rename SDMA debug flagsMarek Olšák2020-01-064-9/+9
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-By: Timur Kristóf <[email protected]>
* panfrost: Handle PIPE_FORMAT_R10G10B10A2_USCALEDAlyssa Rosenzweig2020-01-061-0/+2
| | | | | | | | | | Same format code as UINT... might be different in how it's fed into a shader but we'll deal with that when we get there. Fixes dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.usigned_int2_10_10_10.components4_vec2_quads1 Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Report MSAA 4x supported for dEQPAlyssa Rosenzweig2020-01-061-1/+10
| | | | | | | | | Fixes dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64 We'll have to actually implement multisampling next, but hey. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Cleanup tiling selection logicAlyssa Rosenzweig2020-01-061-13/+14
| | | | | | | | | | | | Make it a lot more obvious what we're doing and fix more than a few corner cases in the process. Fixes dEQP-GLES3.functional.buffer.map.write.render_as_index_array.pixel*, and likely others. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Implement sRGB blend shadersAlyssa Rosenzweig2020-01-062-8/+16
| | | | | | | | | | | | | We use the lowering in nir_format_convert. There are native ops for this so this is far from optimal and not remotely efficient but as with most blend shader things right now, it's hard enough to get it working, so let's focus on that for now. We'll make it fast later (once we have GLES3 stable, we can start optimizing these things). Fixes dEQP-GLES3.functional.fragment_ops.blend.fbo_srgb.* Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Support rendering to non-zero Z/S layersAlyssa Rosenzweig2020-01-061-5/+5
| | | | | | | Fixes abort in STK's shadow implementation. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Texture from Z32F_S8 as R32FAlyssa Rosenzweig2020-01-061-0/+4
| | | | | | | | | Z32F_S8 becomes Z32F in texturing, which in turn just becomes R32F. Fixes dEQP-GLES3.functional.texture.format.sized.*.depth32f_stencil8* Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* iris/query: Implement PIPE_QUERY_GPU_FINISHEDDanylo Piliaiev2020-01-061-0/+17
| | | | | | | Implementation is similar to radeonsi in 5f1cef76 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: use uint-samplers for sampling stencil buffersErik Faye-Lund2020-01-061-4/+6
| | | | | | | Otherwise, we end up mismatching the sampler types when rendering. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/surface: use uint16_t for mipmap level pitchesSamuel Pitoiset2020-01-061-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* etnaviv: fix incorrectly failing vertex size assertJonathan Marek2020-01-051-1/+1
| | | | | | | | | Changes the assert to match the comment above. This assert was failing in some cases while running darkplaces. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* lima: fix PP stream terminator sizeVasily Khoruzhick2020-01-051-1/+3
| | | | | | | | | | PP stream terminator size seems to be 4 words, it worked with full PP stream because we align stream beginning to 32 bytes and BO is initialized with zeroes. But with partial PP stream it sometimes break if for new PP stream we reuse BO that has non-zero value at this place. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: don't reload and redraw tiles that were not updatedVasily Khoruzhick2020-01-053-7/+67
| | | | | | | | | We don't need to reload and redraw some tiles if framebuffer was not cleared and scissor test was enabled for some of draws. This simple optimization fixes cursor lag in X11 Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: postpone PP stream generationVasily Khoruzhick2020-01-051-11/+17
| | | | | | | | | This commit postpones PP stream generation till job is submitted. Doing that this late allows us to skip reloading and redrawing tiles that were not updated. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/parser: Fix VS cmd stream parserAndreas Baierl2020-01-051-2/+2
| | | | | | | prefetch is int, not bool. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* lima/parser: Fix rsw parserAndreas Baierl2020-01-051-2/+0
| | | | | | | Drop assert as it is not necessary and used wrong anyway. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* anv: Only enable EWA LOD algorithm when doing anisotropic filtering.Kenneth Graunke2020-01-041-1/+2
| | | | | | | | | Updated documentation renames "Anisotropic Algorithm" to "LOD Algorithm" and adds a note for Gen9+ saying "The EWA Algorithm should only be enabled for Anisotropic Filtering modes." and indicating that the extra accuracy shouldn't be necessary for other modes, and comes at a cost. Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Allow HiZ for copy_region sourcesKenneth Graunke2020-01-043-5/+18
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Allow HiZ for glCopyImageSubData sourcesJason Ekstrand2020-01-041-0/+9
| | | | | | | v2 (Ken): Handle platforms without sampler support for HiZ Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> [v2 changes]
* anv: Allow HiZ in TRANSFER_SRC_OPTIMAL on Gen8-9Jason Ekstrand2020-01-042-11/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Use the source format when using blorp_copy with HiZJason Ekstrand2020-01-041-1/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Don't resolve HiZ unless we're reinterpretingJason Ekstrand2020-01-041-1/+1
| | | | | | | | | This eliminates 50% of pixels (2M) rendered for a blit in GS:GO. This accounts for 3% of pixels rendered in the game. Total GPU clocks for the first 900 frames of CSGO improves by 1%. Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Allow reading with HiZJason Ekstrand2020-01-042-2/+12
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Stop whacking Z24 depth to BGRA8Jason Ekstrand2020-01-041-11/+0
| | | | | | | | | The shader code required to do this is int(sat(x) * UINT24_MAX) which isn't really worth all the effort to avoid. Doing the format conversion, on the other hand, prevents us from sampling with HiZ which is something that we very much want on gen8-9 where we can. Reviewed-by: Kenneth Graunke <[email protected]>
* etnaviv: move descriptor based texture structsChristian Gmeiner2020-01-042-40/+31
| | | | | | | | This moves the descriptor based texture structs and their helpers into the only user. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* etnaviv: move state based texture structsChristian Gmeiner2020-01-042-49/+42
| | | | | | | | This moves the state based texture structs and their helpers into the only user. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* panfrost: Fix Android buildRoman Stratiienko2020-01-041-0/+1
| | | | | | | Include missing `encoder/pan_props.c` into the build. Signed-off-by: Roman Stratiienko <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* mesa/st: glsl_to_nir: don't lower atomics to SSBOs if driver supports HW atomicsGert Wollny2020-01-041-2/+3
| | | | | | | | | | | | | | At least on r600 HW atomic operations are way less expensive than SSBO atomic operations. v2: use st->has_hw_atomics (Erik Anholt) v3: remove second invocation of atomic to ssbo lowering (Erik Anholt) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600: Delete vertex buffer only if there is actually a shader stateGert Wollny2020-01-041-1/+2
| | | | | | | Fixes: gl-2.0-vertexattribpointer Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600: Make SID and unsigned valueGert Wollny2020-01-041-1/+1
| | | | | | | | | The value is never negative, and makeing it unsigned fixes some warnings Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600: Fix maximum line widthGert Wollny2020-01-041-4/+1
| | | | | | | | | | | | | | | | | | | There are only 13 bits available to store the line width, hence it can't be larger than 8191 v2: Add Fixes tag v3: - Unify value since for all r600 archs (Konstantin Kharlamov) - Correct the value the line width value is emitted as a 12.4 fixed point value of 1/2 line width on r600-r700 and as 8 * line width on Evergreen and newer. Fixes: 06bfb2d28f7adca7edc6be9c210a7a3583023652 r600: fork and import gallium/radeon Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600/sb: Correct SB disassambler for better debuggingGert Wollny2020-01-042-1/+8
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600: Make it possible to include r600_asm.h in a C++ fileGert Wollny2020-01-041-0/+9
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* r600: Add functions to dump the shader infoGert Wollny2020-01-044-0/+211
| | | | | | | | This will be helpful to compare TGSI and NIR code path, Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Konstantin Kharlamov <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* gallium: tgsi_from_mesa - handle VARYING_SLOT_FACEGert Wollny2020-01-041-0/+4
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* nir: make nir_get_texture_size/lod available outside nir_lower_texGert Wollny2020-01-043-110/+117
| | | | | | | | This functions can be useful in other places. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* gallium/tgsi_from_mesa: Add 'extern "C"' to be able to include from C++Gert Wollny2020-01-041-0/+9
| | | | | | | | The r600/nir backend is in C++ and needs to include this file. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
* spirv: Fix glsl type assert in spir2nir.Bas Nieuwenhuizen2020-01-041-0/+4
| | | | | | Fixes: 624789e3708 "compiler/glsl: handle case where we have multiple users for types" Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* etnaviv: use a better name for FE_VERTEX_STREAM_UNK14680Christian Gmeiner2020-01-042-2/+2
| | | | Signed-off-by: Christian Gmeiner <[email protected]>
* radv: Only use the gfx mipmap level offset/pitch for linear textures.Bas Nieuwenhuizen2020-01-041-2/+6
| | | | | | | | | | | | | | | | The tiled-case is non-sensical for non-base mips, but Vulkan requires that this function handles it but at the same time does not require returning anything useful. So we can basically return anything. Correct tiled pitch and offset are still required for our own WSI and in the future getting the layouts of images with DRM format modifiers. Both don't have to deal with images with more than 1 level though. Fixes: 824bd0830e8 "radv: return the correct pitch for linear mipmaps on GFX10" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304 Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Revert "amd/common: Always initialize gfx9 mipmap offset/pitch."Bas Nieuwenhuizen2020-01-042-5/+7
| | | | | | | | | This reverts commit 973181c06cca3fe232c3a435abde31f2fc1b81ef. Requested by Marek. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* iris: Delete remnants of the unimplemented ASTC 5x5 workaroundKenneth Graunke2020-01-034-38/+10
| | | | | | | | I copy and pasted some of the boilerplate but never the implementation. For now, ASTC 5x5 is disabled and faked via uncompressed RGBA; let's delete these remnants until such a time when we implement it properly. Reviewed-by: Tapani Pälli <[email protected]>
* iris: Disable ASTC 5x5 support on Gen9 for now.Kenneth Graunke2020-01-031-0/+8
| | | | | | | | | | | | | | | Intel Gen9 hardware has some nasty restrictions where ASTC 5x5 formats and color compression can't both live in the sampler cache at the same time. To properly support it, we have to track which of those exist in the cache and flush ASTC out or resolve away compression. As far as I'm aware, very little uses ASTC 5x5 textures, so instead of replicating all that for iris, we simply turn it off and rely on the Gallium fallback mechanism to fake it via uncompressed RGBA. This should avoid GPU hangs any time people use ASTC 5x5 with CCS. Reviewed-by: Tapani Pälli <[email protected]>
* st/mesa: Allow ASTC5x5 fallbacks separately from other ASTC LDR formats.Kenneth Graunke2020-01-036-3/+23
| | | | | | | | | This patch allows us to fake ASTC 5x5 specifically, while leaving the other ASTC LDR formats with native support. I plan to use this in iris, at least for the time being. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* etnaviv: use nir_lower_clip_halfz instead of open-codingErik Faye-Lund2020-01-031-20/+3
| | | | | | | | We already have a helper for this, so let's use that instead of rolling our own version. Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Paul Cercueil <[email protected]>
* nir/zink: move clip_halfz-lowering to common codeErik Faye-Lund2020-01-035-54/+82
| | | | | | | | Etnaviv also does the same thing, so let's try to avoid repetition here, and use the same for it code as well. Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Paul Cercueil <[email protected]>
* zink: remove unused code-path in lower_pos_writeErik Faye-Lund2020-01-031-14/+8
| | | | | This code is never reached, because we don't call nir_lower_io before lowering this. So let's get rid of it.
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