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* glsl/nir: Only claim to handle intrinsic functionsJason Ekstrand2018-06-221-23/+2
* nir: add deref lowering sanity checkingRob Clark2018-06-2236-0/+85
* anv,i965,radv,st,ir3: Call nir_lower_deref_instrsJason Ekstrand2018-06-2210-3/+24
* nir/deref: Add some deref cleanup functionsJason Ekstrand2018-06-222-0/+57
* nir: Add helpers for working with deref instructionsJason Ekstrand2018-06-225-0/+363
* nir: Add deref sources to texture instructionsJason Ekstrand2018-06-222-0/+8
* nir: Add _deref versions of all of the _var intrinsicsJason Ekstrand2018-06-224-1/+144
* nir/builder: Add deref building helpersJason Ekstrand2018-06-221-0/+106
* nir: Add a deref instruction typeJason Ekstrand2018-06-229-13/+580
* nir/validate: Rework intrinsic type validationJason Ekstrand2018-06-221-31/+31
* nv50/ir: only avoid spilling constrained def if a mov is addedKarol Herbst2018-06-231-2/+2
* radv: always check the return error when submitting a CSSamuel Pitoiset2018-06-221-5/+11
* radv: check the return values of radv_signal_fence()Samuel Pitoiset2018-06-221-2/+7
* radv: change the returned error in radv_signal_fence()Samuel Pitoiset2018-06-221-2/+1
* freedreno: a2xx: fix clear colorJonathan Marek2018-06-221-1/+1
* freedreno: a2xx: fix crash when freeing contextJonathan Marek2018-06-221-0/+2
* freedreno: a2xx: fix crash on first clearJonathan Marek2018-06-221-4/+4
* freedreno: add a20xJonathan Marek2018-06-227-31/+85
* freedreno: a2xx: increase size of the offset field in instr_fetch_vtx_tJonathan Marek2018-06-221-4/+2
* v3d: Don't forget to initialize the buffer offset of a new winsys handle.Eric Anholt2018-06-211-0/+1
* v3d, vc4: Disable valgrind checking of CLE inputs when NDEBUG is set.Eric Anholt2018-06-211-0/+2
* mesa: fix glGetInteger64v for arrays of integersMarek Olšák2018-06-211-1/+1
* ac/surface: disallow rotated micro tile modeMarek Olšák2018-06-211-2/+19
* radeonsi: fix occlusion queries with 16x AA without FBO attachments on StoneyMarek Olšák2018-06-211-1/+9
* radeonsi: handle non-clearable DCC buffers as MSAA resolve dstMarek Olšák2018-06-212-1/+6
* radeonsi: disable DCC MSAA for 128bpp formats on StoneyMarek Olšák2018-06-211-0/+5
* mesa: fix GLES 3.1 version calculationRob Clark2018-06-211-1/+2
* freedreno/a5xx: MSAARob Clark2018-06-2114-42/+89
* freedreno: update generated headersRob Clark2018-06-218-41/+53
* freedreno/ir3: txf_ms supportRob Clark2018-06-213-7/+51
* freedreno/a5xx: fix gpu hangs with large compute shadersRob Clark2018-06-211-3/+11
* freedreno/ir3: fix base_vertexRob Clark2018-06-211-0/+1
* i965: Link uniforms of SPIR-V programs using the NIR linkerEduardo Lima Mitev2018-06-211-0/+6
* i965: Setup glsl uniforms by index rather than name matchingNeil Roberts2018-06-211-13/+37
* i965: account for NIR uniforms without nameEduardo Lima Mitev2018-06-212-8/+5
* i965: Update TexturesUsed after linking the shadersNeil Roberts2018-06-211-1/+3
* i965: Build SPIR-V programs' resource list using NIREduardo Lima Mitev2018-06-211-1/+7
* nir/linker: Add nir_build_program_resource_list()Eduardo Lima Mitev2018-06-214-0/+72
* compiler/link: move add_program_resource to linker_utilAlejandro Piñeiro2018-06-215-56/+91
* nir/linker: Set the uniform initial valuesNeil Roberts2018-06-215-0/+298
* nir/linker: Add gl_nir_link_uniforms()Eduardo Lima Mitev2018-06-214-0/+506
* compiler/link: add linker_util.h, move linker_error/warning to itAlejandro Piñeiro2018-06-216-14/+48
* spirv: Set nir_variable->explicit_bindingNeil Roberts2018-06-212-0/+3
* spirv: Get rid of vtn_variable_mode_image/samplerNeil Roberts2018-06-215-39/+20
* spirv: translate default-block uniformsNicolai Hähnle2018-06-212-10/+16
* nir/types: Add a utility wrapper to glsl_type::sampler_index()Eduardo Lima Mitev2018-06-212-0/+8
* nir/types: Add a glsl_get_component_slots() utilityEduardo Lima Mitev2018-06-212-0/+7
* nir/lower_samplers: Limit assert to GLSL shader programsEduardo Lima Mitev2018-06-211-1/+2
* nir: Add explicit_binding to nir_variableNeil Roberts2018-06-212-0/+6
* mesa/main: add NULL name check when searching for a resource nameAlejandro Piñeiro2018-06-211-0/+5
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