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* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-076-8/+8
* compiler/glsl: do not downcast list sentinelNicolai Hähnle2016-05-071-1/+4
* mesa/main: fix another undefined left shiftNicolai Hähnle2016-05-071-1/+1
* mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle2016-05-071-30/+30
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
* vc4: Make sure that we don't overwrite the signal for PROG_END.Eric Anholt2016-05-061-0/+8
* nvc0: unreference images when the context is destroyedSamuel Pitoiset2016-05-061-0/+4
* nir: Remove spurious return from void function.Jose Fonseca2016-05-061-2/+0
* radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4Marek Olšák2016-05-061-1/+2
* r600g: use the hw MSAA resolving if formats are compatibleMarek Olšák2016-05-061-1/+2
* Revert "i965: Switch to scalar TCS by default."Kenneth Graunke2016-05-051-1/+1
* st/omx/enc: fix incorrect reference picture order for B framesLeo Liu2016-05-051-7/+12
* i965/fs: Move handling of samples_identical into the switch statementJason Ekstrand2016-05-051-21/+19
* i965/fs: Simplify texture destination fixupsJason Ekstrand2016-05-051-21/+11
* i965/fs: stop inclinding glsl/ir.h in brw_fs.hJason Ekstrand2016-05-052-1/+1
* i965/fs: Merge nir_emit_texture and emit_textureJason Ekstrand2016-05-053-238/+162
* nir: remove now-unused nir_foreach_block*_call()Connor Abbott2016-05-051-38/+0
* vc4: fixup for new nir_foreach_block()Connor Abbott2016-05-054-48/+20
* ir3: fixup for new nir_foreach_block()Connor Abbott2016-05-051-30/+21
* nir/lower_double_ops: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-23/+9
* nir/lower_double_pack: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-26/+21
* nir/gather_info: fixup for new foreach_block()Jason Ekstrand2016-05-051-5/+5
* nir/lower_two_sided_color: fixup for new foreach_block()Connor Abbott2016-05-051-3/+5
* nir/lower_tex: fixup for new foreach_block()Connor Abbott2016-05-051-25/+22
* nir/lower_outputs_to_temporaries: fixup for new foreach_block()Connor Abbott2016-05-051-16/+12
* i965: Switch to scalar TCS by default.Kenneth Graunke2016-05-051-1/+1
* nir: Optimize out stores of undefs.Kenneth Graunke2016-05-051-0/+30
* nir: Replace vecN(undef, undef, ...) with a single undef.Kenneth Graunke2016-05-051-0/+33
* nir: Rename opt_undef_alu to opt_undef_csel; update comments.Kenneth Graunke2016-05-051-12/+13
* i965: Rework passthrough TCS checks.Kenneth Graunke2016-05-054-2/+5
* swr: [rasterizer core] Faster modulo operator in ProcessVertsTim Rowley2016-05-051-1/+4
* swr: [rasterizer] Small warning cleanupTim Rowley2016-05-052-8/+4
* swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macrosTim Rowley2016-05-052-14/+52
* swr: [rasterizer] Miscellaneous backend changesTim Rowley2016-05-053-22/+31
* swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT formatTim Rowley2016-05-053-7/+41
* swr: [rasterizer jitter] Fix printing bugs for tracing.Tim Rowley2016-05-051-81/+24
* swr: [rasterizer memory] Add missing store tiles functionTim Rowley2016-05-051-1/+4
* swr: [rasterizer jitter] Add asserts for supported formats in fetch shaderTim Rowley2016-05-051-0/+2
* swr: [rasterizer core] Fix thread allocationTim Rowley2016-05-051-17/+47
* swr: [rasterizer core] Fix threadviz support in bucketsTim Rowley2016-05-053-12/+14
* swr: [rasterizer] Whitespace cleanup and misc changesTim Rowley2016-05-055-5/+2
* radeonsi: mark descriptor loads as using dynamically uniform indicesNicolai Hähnle2016-05-051-5/+17
* i965/fs: Don't follow pow with an instruction with two dest regs.Matt Turner2016-05-051-0/+18
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