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* glsl: Make ir_variable::num_state_slots and ir_variable::state_slots privateIan Romanick2014-09-3010-56/+78
* glsl: Make ir_variable::max_ifc_array_access privateIan Romanick2014-09-305-22/+53
* glsl: Store ir_variable::depth_layout using 3 bitsIan Romanick2014-09-301-10/+9
* glsl: Replace ir_variable::warn_extension pointer with an 8-bit indexIan Romanick2014-09-303-10/+31
* glsl: Use accessors for ir_variable::warn_extensionIan Romanick2014-09-303-7/+30
* glsl: Eliminate unused built-in variables after compilationIan Romanick2014-09-304-0/+104
* glsl: Validate that built-in uniforms have backing stateIan Romanick2014-09-301-0/+8
* vc4: Don't forget to store stencil along with depth when storing either.Eric Anholt2014-09-301-1/+1
* llvmpipe: Reuse llvmpipes LLVMContext in the draw context.Mathias Fröhlich2014-09-305-9/+31
* llvmpipe: Make a llvmpipe OpenGL context thread safe.Mathias Fröhlich2014-09-304-18/+40
* llvmpipe: Use two LLVMContexts per OpenGL context instead of a global one.Mathias Fröhlich2014-09-3013-31/+40
* i965/brw_reg: Make the accumulator register take an explicit width.Jason Ekstrand2014-09-303-10/+15
* llvmpipe: move lp_jit_screen_init() call after allocation of screen objectBrian Paul2014-09-301-3/+5
* tgsi: fix Semantic.Name assignment in tgsi_transform_input_decl()Brian Paul2014-09-301-1/+1
* util: simplify PIPE_TEXTURE_CUBE case in util_max_layer()Brian Paul2014-09-301-2/+3
* softpipe: don't special case PIPE_TEXTURE_CUBE in softpipe_resource_layout()Brian Paul2014-09-301-2/+3
* llvmpipe: remove special case for PIPE_TEXTURE_CUBE in llvmpipe_texture_layout()Brian Paul2014-09-301-3/+6
* gallium: add doc note about cube textures and can_create_resource()Brian Paul2014-09-301-0/+2
* st/mesa: remove unneded PIPE_TEXTURE_CUBE check in st_texture_create()Brian Paul2014-09-301-1/+1
* mesa: Drop the always-software-primitive-restart paths.Eric Anholt2014-09-305-58/+8
* gallium: Drop software-only primitive restart support.Eric Anholt2014-09-301-3/+2
* i965/fs: Properly calculate the number of instructions in calculate_register_...Jason Ekstrand2014-09-301-1/+3
* i965/fs: Use the GRF for FB writes on gen >= 7Jason Ekstrand2014-09-306-71/+142
* i965/fs: Handle COMPR4 in LOAD_PAYLOADJason Ekstrand2014-09-302-1/+36
* i965/fs: Constant propagate into LOAD_PAYLOADJason Ekstrand2014-09-301-0/+1
* i965/fs: Add split_virtual_grfs and compute_to_mrf after lower_load_payloadJason Ekstrand2014-09-301-0/+2
* i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instructionJason Ekstrand2014-09-304-29/+28
* i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructionsJason Ekstrand2014-09-304-16/+24
* i965/fs: Use the GRF for UNTYPED_ATOMIC instructionsJason Ekstrand2014-09-306-25/+36
* i965/fs: Add a function for getting a component of a 8 or 16-wide registerJason Ekstrand2014-09-301-0/+10
* i965/fs: Use the instruction execution size directly for texture generationJason Ekstrand2014-09-301-3/+10
* i965/fs: Use exec_size instead of force_uncompressed in dump_instructionJason Ekstrand2014-09-301-6/+7
* i965/fs: Use instruction execution sizes instead of heuristicsJason Ekstrand2014-09-303-23/+10
* i965/fs: Use instruction execution sizes to set compression stateJason Ekstrand2014-09-301-6/+19
* i965/fs: Remove unneeded uses of force_uncompressedJason Ekstrand2014-09-303-25/+9
* i965/fs: Derive force_uncompressed from instruction exec_sizeJason Ekstrand2014-09-301-0/+3
* i965/fs: Make fs_reg::effective_width take fs_inst* instead of fs_visitor*Jason Ekstrand2014-09-303-37/+43
* i965/fs: Better guess the width of LOAD_PAYLOADJason Ekstrand2014-09-301-2/+9
* i965/fs: Add an exec_size field to fs_instJason Ekstrand2014-09-305-32/+126
* i965/fs: Determine partial writes based on the destination widthJason Ekstrand2014-09-302-5/+3
* i965/fs: Fix a bug in register coalesceJason Ekstrand2014-09-301-0/+17
* i965/fs: Rework GEN5 texturing code to use fs_reg and offset()Jason Ekstrand2014-09-301-39/+38
* i965/fs_reg: Allocate double the number of vgrfs in SIMD16 modeJason Ekstrand2014-09-309-157/+371
* i965/fs: Handle printing of registers better.Jason Ekstrand2014-09-301-2/+6
* i965: Explicitly set widths on gen5 math instruction destinations.Jason Ekstrand2014-09-301-1/+1
* i965/fs: Make half() divide the register width by 2 and use it moreJason Ekstrand2014-09-302-5/+13
* i965/fs: Add a concept of a width to fs_regJason Ekstrand2014-09-302-4/+78
* i965/fs: A little harmless refactoring of register_coalesceJason Ekstrand2014-09-301-7/+7
* i965/brw_reg: Add a firsthalf function and use it in the generatorJason Ekstrand2014-09-302-29/+44
* i965/fs: Copy propagate partial reads.Jason Ekstrand2014-09-302-20/+64
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