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* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1
* glx: Fix __glXWireToEvent for BufferSwapCompleteAdam Jackson2015-08-181-0/+3
* radeon/uvd: remove unused variablesGrazvydas Ignotas2015-08-181-4/+1
* nouveau: recognize tess stages in nouveau_compilerMarcos Paulo de Souza2015-08-171-0/+4
* tgsi: fix parsing of tessellation shader inputs/outputsMarcos Paulo de Souza2015-08-171-1/+16
* tgsi: set implicit array size for tess stagesMarcos Paulo de Souza2015-08-171-1/+5
* mesa: move non-generic samples validationTimothy Arceri2015-08-182-9/+10
* mesa: check samples > 0 for glTex*MultisampleTimothy Arceri2015-08-181-0/+5
* i965/vec4/nir: Emit single MOV to generate a scalar constant.Matt Turner2015-08-171-3/+18
* freedreno/a3xx: add s3tc texture format supportIlia Mirkin2015-08-171-0/+9
* freedreno/a3xx: fix up logic for handling block formatsIlia Mirkin2015-08-173-5/+7
* freedreno/a3xx: double the polygon offset valueIlia Mirkin2015-08-171-1/+1
* nvc0: implement the color buffer 0 is integer rule for alpha-to-one/covIlia Mirkin2015-08-173-11/+22
* mesa: Raise INVALID_VALUE from glCreateShaderProgramv if count < 0Marta Lofstedt2015-08-171-0/+9
* mesa: AtomicBufferBindings should be initialized to zero.Marta Lofstedt2015-08-171-2/+2
* mesa: fix target error checking in glGetTexLevelParameterTapani Pälli2015-08-171-7/+25
* gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin2015-08-171-7/+10
* mesa: rename texture function now that its staticTimothy Arceri2015-08-171-31/+31
* glsl: add missing MS sampler builtin types for GLSL ES 3.10Tapani Pälli2015-08-172-6/+7
* mesa: Implement glMemoryBarrierByRegionMarta Lofstedt2015-08-174-2/+56
* nvc0: program smooth line width when multisampling is enabledIlia Mirkin2015-08-171-1/+1
* nvc0: bind a fake tess control program when there isn't one availableIlia Mirkin2015-08-174-8/+44
* gm107/ir: avoid letting the lowering pass get out of syncIlia Mirkin2015-08-172-88/+5
* nv50,nvc0: take level into account when doing eng2d multi-layer blitsIlia Mirkin2015-08-172-8/+20
* st/mesa: also move yoffset to zoffset for 1d array texturesIlia Mirkin2015-08-171-0/+2
* nir: Add a glsl_uint_type() wrapper.Kenneth Graunke2015-08-162-0/+7
* freedreno/a3xx: add per-texture seamless cubemap controlIlia Mirkin2015-08-162-1/+2
* freedreno/a4xx: add cube map array supportIlia Mirkin2015-08-154-4/+14
* freedreno/a4xx: fix srgb render targetsRob Clark2015-08-153-8/+22
* freedreno: update generated headersRob Clark2015-08-155-14/+30
* freedreno: expose OES exts for float linear filteringIlia Mirkin2015-08-141-2/+4
* nvc0: disable tessellation on maxwellIlia Mirkin2015-08-141-2/+5
* nir: Add support for CSE on textures.Eric Anholt2015-08-141-4/+39
* nir: Zero out texture instructions when creating them.Eric Anholt2015-08-141-1/+1
* vc4: Move all of our fixed function fragment color handling to NIR.Eric Anholt2015-08-146-388/+538
* vc4: Add a helper for making driver-specific NIR load_uniform for GL stateEric Anholt2015-08-142-2/+30
* nir: Don't try to scalarize unpack ops.Eric Anholt2015-08-141-0/+15
* nir: Add a nir_opt_undef() to handle csels with undef.Eric Anholt2015-08-144-0/+108
* gm107/ir: indirect handle goes first on maxwell alsoIlia Mirkin2015-08-141-8/+4
* nv30: add depth bounds test support for hw that has itIlia Mirkin2015-08-143-2/+14
* nv50: add depth bounds test supportIlia Mirkin2015-08-143-2/+12
* nvc0: add depth bounds test supportIlia Mirkin2015-08-143-2/+9
* radeonsi: revert a wrong DB bug workaround for VIMarek Olšák2015-08-141-4/+0
* radeon/uvd: implement HEVC supportBoyuan Zhang2015-08-143-17/+298
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-143-1/+5
* radeon/vce: implement VCE dual instance supportLeo Liu2015-08-143-5/+30
* radeon/video: config encode stacked frame number based on HWLeo Liu2015-08-141-0/+2
* radeon/vce: make reloc offset signedChristian König2015-08-144-6/+6
* radeon/vce: add config task and put task info into encoder v2Leo Liu2015-08-144-33/+47
* radeon/vce: fix VCE fail after rebaseLeo Liu2015-08-141-8/+6
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