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* panfrost: Document MALI_WRITES_GLOBAL bitAlyssa Rosenzweig2020-06-033-1/+9
| | | | | | | We've been setting this unconditionally -- oops! Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5300>
* panfrost: Update MALI_EARLY_Z descriptionAlyssa Rosenzweig2020-06-031-5/+5
| | | | | | | | Via the ES3.1 early-z testing force, I've confirmed this bit is e-z. I've also confirmed e-z must be disabled for global writes, as expected. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5300>
* iris: remove unused iris_bo->swizzle_modeMarcin Ślusarz2020-06-032-24/+0
| | | | | | | Signed-off-by: Marcin Ślusarz <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5313>
* aco: sign-extend input/identity for 16-bit subgroup ops on GFX6-GFX7Samuel Pitoiset2020-06-031-0/+3
| | | | | | | | | 16-bit subgroup ops are implemented with 32-bit instructions on GFX6-GFX7. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5227>
* aco: fix subdword copies on GFX6-GFX7Samuel Pitoiset2020-06-031-7/+11
| | | | | | | | SDWA is only GFX8+. Use v_mov_b32 since the upper 16 bits don't matter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5227>
* aco: implement 16-bit nir_intrinsic_quad_* on GFX6-GFX7Samuel Pitoiset2020-06-031-2/+8
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5227>
* aco: implement 16-bit reduce operations on GFX6-GFX7Samuel Pitoiset2020-06-031-6/+54
| | | | | | | | No fp16 on GFX6-GFX7. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5227>
* pan/bi: Handle vectorized load_constAlyssa Rosenzweig2020-06-031-4/+13
| | | | | | | In preparation for 16-bit vectors. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5307>
* pan/bi: Passthrough second argument of F32_TO_F16Alyssa Rosenzweig2020-06-031-0/+20
| | | | | | | | At the NIR level this is a second vector source of the first (only) argument; at the BIR level this is a pair of scalars. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5307>
* pan/bi: Pack second argument of F32_TO_F16Alyssa Rosenzweig2020-06-031-4/+6
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5307>
* pan/bi: Fix SEL.16 swizzleAlyssa Rosenzweig2020-06-031-4/+4
| | | | | | | 2 scalar arguments, not 1 vector. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5307>
* pan/bi: Handle SEL with vec3 16-bitAlyssa Rosenzweig2020-06-031-0/+4
| | | | | | | Otherwise we end up with a missing argument. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5307>
* panfrost: Passthrough NATIVE loads/storesAlyssa Rosenzweig2020-06-031-0/+18
| | | | | | | | Now that we handle load_output directly, this works for e.g. RGB565 on Midgard. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Handle regular nir_intrinsic_load_outputAlyssa Rosenzweig2020-06-031-17/+22
| | | | | | | | Instead of the vendored version. Only for blend shaders at the moment, frag shaders fb_fetch has a lot more going on. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Allow f2u8 and friends thruAlyssa Rosenzweig2020-06-031-3/+3
| | | | | | | | Now that we can handle destination sizes directly, this keeps us from needing to chew through so many conversions. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Handle f2u8Alyssa Rosenzweig2020-06-031-1/+3
| | | | | | | This is similar to f2u16. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Fold roundmode into applicable instructionsAlyssa Rosenzweig2020-06-031-3/+20
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Implement *_rtz conversions with roundmodeAlyssa Rosenzweig2020-06-031-12/+22
| | | | | | | Use rte as the canonical type. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Lower roundmodesAlyssa Rosenzweig2020-06-031-1/+14
| | | | | | | So now we can use the IR field semantically. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Add opcode roundmode propertyAlyssa Rosenzweig2020-06-032-4/+11
| | | | | | | When the output is rounded in a specified direction. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Add roundmode enumAlyssa Rosenzweig2020-06-032-0/+10
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* pan/mdg: Distinguish blend shaders in internal shader-dbAlyssa Rosenzweig2020-06-031-0/+1
| | | | | | | | Since these shaders are purely internal, the optimization criteria are a bit different, so it's worth calling attention to this when dumping. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>
* panfrost: Only use AFBC YTR with RGB and RGBAIcecream952020-06-032-4/+12
| | | | | | | The "lossless colorspace transform" is lossy for R and RG formats. Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5293>
* panfrost: Decode AFBC flag bitsIcecream952020-06-033-12/+30
| | | | | Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5293>
* glsl: when NIR linker enable use it to resize uniform arraysTimothy Arceri2020-06-032-13/+24
| | | | | | | | | | | | | | | | | | | | | | | Here we turn on uniform array resizing in the NIR linker and disable the GLSL IR resizing pass when the NIR linker is enabled. This will potentially make uniform arrays smaller due to NIR optimising away more uniform uses. Shader-db results (SKL): total instructions in shared programs: 14947192 -> 14944093 (-0.02%) instructions in affected programs: 138088 -> 134989 (-2.24%) helped: 822 HURT: 4 total cycles in shared programs: 324868402 -> 324794597 (-0.02%) cycles in affected programs: 3904170 -> 3830365 (-1.89%) helped: 2333 HURT: 1485 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* glsl: gather uniform dereference info before main linking loopTimothy Arceri2020-06-031-13/+24
| | | | | | | | | We want to gather information for all stages here before the main linking loop. In the following patch we will use to information to reduce the size of uniform arrays where possible. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* glsl: add update_array_sizes() helper to the NIR uniform linkerTimothy Arceri2020-06-031-0/+103
| | | | | | | | | This will be used to reduce the size of uniform arrays and replace the current glsl ir pass. Doing this in NIR allows us to better optimise the size of uniform arrays. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* glsl: add struct to gather more info about uniform array accessTimothy Arceri2020-06-031-8/+29
| | | | | | | | This will be used in the following patches to allow the linker to resize uniform arrays based on array dereferences. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* util: add BITSET_LAST_BIT() helperTimothy Arceri2020-06-031-0/+14
| | | | | | | This is the reverse of BITSET_FFS() Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* i965: call brw_nir_lower_uniforms() after uniform linking is completeTimothy Arceri2020-06-031-2/+1
| | | | | | | | | | | | | | | | i965 currently uses the NIR uniform linker for spirv support. Until now the only reason there has been no issue with calling the lowering pass before the linker is because no garbage collection is done between the calls. An upcoming change to the linker will add an optimisation to resize unform arrays where possible. Because lowering causes the array defs to no longer be used the new optimisation ends up resizing the arrays to 0. To fix this we move the lowering call after the linking calls. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4910>
* gbm: document that gbm_bo_map exposes a linear viewSimon Ser2020-06-031-0/+5
| | | | | | | | | | Drivers (Gallium, i965) expose a linear view of the buffer via gbm_bo_map. Signed-off-by: Simon Ser <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5238>
* glsl: Don't replace lrp pattern with lrp if arguments are not floatsDanylo Piliaiev2020-06-031-1/+2
| | | | | | | | | | | | We don't have "lrp(int, int, int)" and validation of ir_triop_lrp fails down the road. Fixes: 8d37e991 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3059 Signed-off-by: Danylo Piliaiev <[email protected]> Tested-by: Witold Baryluk <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5257>
* spirv: Use scoped barriers for SpvOpControlBarrierBoris Brezillon2020-06-031-3/+28
| | | | | | | | | If use_scoped_barrier is set to true, we don't have to split the control and memory barriers. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4900>
* intel/compiler: Extract control barriers from scoped barriersBoris Brezillon2020-06-034-0/+87
| | | | | | | | | | | Add a lowering pass extracting all control barriers embedded in scoped barriers into proper control barriers so we can get rid of the logic inserting control barriers when an SpvOpControlBarrier with WorkGroup scope is parsed in spirv_to_nir(). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4900>
* nir: Replace the scoped_memory barrier by a scoped_barrierBoris Brezillon2020-06-0314-36/+61
| | | | | | | | | | | | | | SPIRV OpControlBarrier can have both a memory and a control barrier which some hardware can handle with a single instruction. Let's turn the scoped_memory_barrier into a scoped barrier which can embed both barrier types. Note that control-only or memory-only barriers can be supported through this new intrinsic by passing NIR_SCOPE_NONE to the unused barrier type. Signed-off-by: Boris Brezillon <[email protected]> Suggested-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4900>
* spirv: Split the vtn_emit_scoped_memory_barrier() logicBoris Brezillon2020-06-031-6/+31
| | | | | | | | | | We are about to add support for scoped control+memory barriers. Let's move the convert from SPIRV to NIR enums logic in helpers so we can easily re-use them. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4900>
* radv: enable zero VRAM for all VKD3D (DX12->VK) gamesSamuel Pitoiset2020-06-031-34/+43
| | | | | | | | | | | To fix rendering issues with Metro Exodus, RE2 and 3 and probably more titles. It seems the default behaviour of DX12 anyways. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3064 Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5262>
* radv: enable zero VRAM for Doom EternalSamuel Pitoiset2020-06-031-0/+3
| | | | | | | | | | | That fixes some rendering issues. Probably some unitialized data from the game. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3064 Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5262>
* glsl/spirv: remove dead uniforms in spirv nir linkerTimothy Arceri2020-06-031-0/+8
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
* glsl: remove dead uniforms in the nir linkerTimothy Arceri2020-06-031-0/+8
| | | | | | | | | | | | | | | | | | | | This is now possible as we do uniform linking via a nir based linker. Shader-db results for IRIS (SKL): total instructions in shared programs: 14947192 -> 14946397 (<.01%) instructions in affected programs: 39498 -> 38703 (-2.01%) helped: 230 HURT: 18 total cycles in shared programs: 324868402 -> 324847058 (<.01%) cycles in affected programs: 706701 -> 685357 (-3.02%) helped: 599 HURT: 449 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
* glsl: add can_remove_uniform() helper to the NIR linkerTimothy Arceri2020-06-031-0/+32
| | | | | | | | | | | This helper reflects the rules we follow in the GLSL IR linker when deciding if we can remove a dead uniform. This check is required to avoid regressions when turning on NIR dead uniform clean up in the following patch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
* nir: add callback to nir_remove_dead_variables()Timothy Arceri2020-06-0323-51/+78
| | | | | | | | | | | | This allows us to do API specific checks before removing variable without filling nir_remove_dead_variables() with API specific code. In the following patches we will use this to support the removal of dead uniforms in GLSL. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
* nir: add glsl_get_ifc_packing() helperTimothy Arceri2020-06-032-0/+8
| | | | | | | | This will be used in the following patch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
* pan/mdg: Don't double-replicate blend on T720Alyssa Rosenzweig2020-06-031-21/+1
| | | | | | | We already do this unconditionally in NIR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5305>
* radv: Use common gfx10_format_table.hBas Nieuwenhuizen2020-06-035-300/+5
| | | | | | | Save some python code and build time, as well as some code duplication. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* radv: Include gfx10_format_table.h only from a single source file.Bas Nieuwenhuizen2020-06-032-12/+11
| | | | | | | | The radeonsi variant has everything in the header, so lets not include it everywhere. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* radeonsi: Define gfx10_format in the common header.Bas Nieuwenhuizen2020-06-036-17/+55
| | | | | | | | | | | | | So we don't have to have multiple definitions of the struct when sharing with radv. While at it put the table properly in a C file so we don't have to deal with multiple definitions, and the struct definition isn't in generated source. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* amd/common,radeonsi: Move gfx10_format_table to common.Bas Nieuwenhuizen2020-06-038-32/+32
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* radeonsi: Explicitly map Z16_UNORM_S8_UINT to None for GFX10.Bas Nieuwenhuizen2020-06-031-0/+1
| | | | | | | | | We should always use separate planes for textures with this format. Fixes: 273ead81f1a "util/format: Add VK_FORMAT_D16_UNORM_S8_UINT." Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* zink: Use store_dest_raw instead of storing an uintErik Faye-Lund2020-06-021-2/+1
| | | | | | | | | I cleaned up the other similar call-sites, but somehow missed this one. There's nothing different with this, so let's also fix this. Fixes: 16339646f03 ("zink/spirv: rename functions a bit") Reviewed-by: Mike Blumenkrantz <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5250>
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