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* lima/ppir: Add fddx and fddyAndreas Baierl2019-08-124-0/+60
* radv: Enable VK_KHR_pipeline_executable_properties.Bas Nieuwenhuizen2019-08-122-1/+7
* radv: Implement radv_GetPipelineExecutableStatisticsKHR.Bas Nieuwenhuizen2019-08-121-0/+103
* radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.Bas Nieuwenhuizen2019-08-121-5/+104
* radv: Implement radv_GetPipelineExecutablePropertiesKHR.Bas Nieuwenhuizen2019-08-121-0/+111
* radv: Keep shader info when needed.Bas Nieuwenhuizen2019-08-124-23/+36
* radv: Add VK_KHR_pipeline_executable_properties in disabled state.Bas Nieuwenhuizen2019-08-121-0/+1
* radv: Use string for nir dumping.Bas Nieuwenhuizen2019-08-124-8/+29
* radv: Get max workgroup size without nir.Bas Nieuwenhuizen2019-08-123-19/+28
* radv: Add utility function to calculate max waves.Bas Nieuwenhuizen2019-08-122-8/+24
* iris/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-0/+110
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
* i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-6/+109
* pan/midgard: Handle 64-bit address in mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-121-1/+36
* pan/midgard: Allocate separate spill indices for lowered movesAlyssa Rosenzweig2019-08-121-6/+4
* pan/midgard: Extend liveness analysis to trinary opsAlyssa Rosenzweig2019-08-121-6/+2
* pan/midgard: Fix load/store pairingAlyssa Rosenzweig2019-08-121-9/+6
* pan/midgard: Implement nir_intrinsic_load_num_work_groupsAlyssa Rosenzweig2019-08-125-0/+21
* pan/midgard: Implement some compute builtinsAlyssa Rosenzweig2019-08-121-0/+28
* pan/midgard: Rename ld_global_id -> ld_compute_idAlyssa Rosenzweig2019-08-122-3/+3
* pan/midgard: Handle partial writes in liveness analysisAlyssa Rosenzweig2019-08-121-9/+5
* pan/midgard: Dump "no spill"?Alyssa Rosenzweig2019-08-121-0/+3
* pan/midgard: Absorb nonexistance sourcesAlyssa Rosenzweig2019-08-121-0/+5
* pan/midgard: Pretty-print destinationsAlyssa Rosenzweig2019-08-121-5/+6
* pan/midgard: Pretty-print unitsAlyssa Rosenzweig2019-08-121-1/+24
* pan/midgard: Print mask in dumped MIRAlyssa Rosenzweig2019-08-121-1/+19
* pan/midgard: Add no_spill flagAlyssa Rosenzweig2019-08-122-6/+15
* pan/midgard: Generalize mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-121-11/+24
* pan/midgard: Implement SSBO accessAlyssa Rosenzweig2019-08-122-11/+115
* pan/midgard: Pipe uniform mask through when spillingAlyssa Rosenzweig2019-08-122-2/+30
* pan/midgard: Clamp sysval component countAlyssa Rosenzweig2019-08-122-5/+9
* pan/midgard: Pass uploaded midgard_instruction throughAlyssa Rosenzweig2019-08-122-5/+7
* pan/midgard: Allow sysval destination overrideAlyssa Rosenzweig2019-08-122-4/+10
* panfrost: Force flush every compute jobAlyssa Rosenzweig2019-08-121-0/+2
* panfrost: Add SSBO system valueAlyssa Rosenzweig2019-08-123-0/+38
* gallium/util: Add u_stream_outputs_for_vertices helperAlyssa Rosenzweig2019-08-121-0/+19
* radeonsi: remove the always_nir optionMarek Olšák2019-08-124-6/+2
* radeonsi/nir: implement default tess level system valuesMarek Olšák2019-08-123-18/+45
* compiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULTMarek Olšák2019-08-124-0/+20
* gallium: add TGSI_SEMANTIC_DEFAULT_OUTER/INNER_LEVELMarek Olšák2019-08-125-12/+19
* tgsi_to_nir: handle tess level inner/outer varyingsMarek Olšák2019-08-121-0/+7
* tgsi_to_nir: add support for the stencil FS outputMarek Olšák2019-08-121-5/+12
* tgsi_to_nir: add support for TEX_LZMarek Olšák2019-08-121-2/+9
* compiler: add SYSTEM_VALUE_USER_DATA_AMDMarek Olšák2019-08-127-0/+23
* compiler: add shader_info.cs.user_data_components_amdMarek Olšák2019-08-123-0/+5
* tgsi_to_nir: add basic compute shader supportMarek Olšák2019-08-121-0/+23
* tgsi_to_nir: add support for LOAD & STORE with SSBOs and imagesMarek Olšák2019-08-121-2/+310
* tgsi_to_nir: make setup_texture_info reusableMarek Olšák2019-08-121-36/+48
* tgsi_to_nir: add support for TXF_LZMarek Olšák2019-08-121-4/+13
* compiler: add shader_info.vs.blit_sgprs_amdMarek Olšák2019-08-123-0/+12
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