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* freedreno/a6xx: fix resource_copy_region()Rob Clark2018-12-131-9/+24
* freedreno: move fd_resource_copy_region()Rob Clark2018-12-133-62/+73
* freedreno/a6xx: more blitter fixesRob Clark2018-12-131-10/+22
* freedreno: update generated headersRob Clark2018-12-138-30/+39
* gallium/aux: add is_unorm() helperRob Clark2018-12-132-0/+24
* freedreno/a6xx: fix blitter crashRob Clark2018-12-131-0/+17
* freedreno/ir3: don't remove unused input componentsRob Clark2018-12-131-1/+7
* freedreno/ir3: fix crashRob Clark2018-12-131-14/+8
* freedreno: also set DUMP flag on shadersRob Clark2018-12-135-20/+22
* freedreno: debug GEM obj namesRob Clark2018-12-1313-21/+91
* freedreno/drm: sync uapi and enable softpinRob Clark2018-12-136-25/+30
* nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2018-12-132-8/+15
* Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt2018-12-131-2/+8
* nir: Print the format of image variables.Eric Anholt2018-12-131-0/+47
* mesa/st: Expose compute shaders when NIR support is advertised.Eric Anholt2018-12-132-8/+14
* radv/xfb: fix counter buffer bounds checks.Dave Airlie2018-12-131-2/+2
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* i965/fs: Implement nir_op_uadd_satIan Romanick2018-12-131-0/+5
* nir: Add a pass for lowering integer division by constantsJason Ekstrand2018-12-134-0/+219
* nir: Add a saturated unsigned integer add opcodeIan Romanick2018-12-131-0/+2
* nir/lower_int64: Add support for [iu]mul_highJason Ekstrand2018-12-132-0/+67
* nir: Allow [iu]mul_high on non-32-bit typesJason Ekstrand2018-12-132-4/+40
* glx: mandate xf86vidmode only for "drm" dri platformsEmil Velikov2018-12-131-2/+4
* nir: remove unused variableAlejandro Piñeiro2018-12-131-1/+0
* virgl: work around bad assumptions in virglrendererErik Faye-Lund2018-12-131-1/+32
* virgl: wrap vertex element state in a structErik Faye-Lund2018-12-132-9/+21
* virgl: simplify virgl_hw_set_index_bufferErik Faye-Lund2018-12-131-3/+2
* virgl: simplify virgl_hw_set_vertex_buffersErik Faye-Lund2018-12-131-4/+2
* radv: don't check if format is depth in radv_image_can_enable_hile()Samuel Pitoiset2018-12-131-1/+0
* radv: check if addrlib enabled HTILE in radv_image_can_enable_htile()Samuel Pitoiset2018-12-131-1/+2
* radv: switch on EOP when primitive restart is enabled with triangle stripsSamuel Pitoiset2018-12-131-2/+1
* radv: allow to skip DCC decompressions with the new predicateSamuel Pitoiset2018-12-131-6/+13
* radv: add a predicate for reflecting DCC decompression stateSamuel Pitoiset2018-12-135-1/+44
* i965/compute: Emit GPGPU_WALKER in genX_state_uploadJordan Justen2018-12-123-130/+105
* i965/genX_state: Add register access functionsJordan Justen2018-12-121-0/+31
* intel: Simplify the half-float packing in image load/store lowering.Eric Anholt2018-12-121-8/+2
* nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2018-12-122-18/+40
* nir: Add some more consts to the nir_format_convert.h helpers.Eric Anholt2018-12-121-7/+6
* nir: detect more induction variablesTimothy Arceri2018-12-131-0/+36
* nir: reword code commentTimothy Arceri2018-12-131-2/+2
* nir: in loop analysis track actual control flow typeTimothy Arceri2018-12-131-13/+21
* nir: add if opt opt_if_loop_last_continue()Danylo Piliaiev2018-12-131-0/+95
* nir: rework force_unroll_array_access()Timothy Arceri2018-12-131-14/+35
* nir: factor out some of the complex loop unroll code to a helperTimothy Arceri2018-12-131-51/+64
* meson: libfreedreno depends upon libdrm (for fence support)Rhys Kidd2018-12-121-3/+1
* nir: Document the function inlining processJason Ekstrand2018-12-121-0/+68
* intel/blorp: Assert that we don't re-layout a compressed surfaceJason Ekstrand2018-12-121-0/+3
* anv/pipeline: Set the correct binding count for compute shadersJason Ekstrand2018-12-121-2/+6
* radv: bump reported version to 1.1.90Samuel Pitoiset2018-12-121-1/+1
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