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* i965: Remove all bits of NRM3 and NRM4 codeIan Romanick2011-08-251-31/+0
* Merge branch 'kasanen-post-process-v2'Brian Paul2011-08-252-0/+90
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| * driconf: Add the PP descriptionsLauri Kasanen2011-08-192-0/+90
* | glsl_to_tgsi: add TXF support. (v2)Dave Airlie2011-08-251-3/+7
* | glsl_to_tgsi: implement TXS/TXQ. (v2)Dave Airlie2011-08-251-9/+18
* | glsl: Implement the GL_ARB_conservative_depth extension.Kenneth Graunke2011-08-251-0/+1
* | Change return type of try_emit_* methods to bool.Kai Wasserbäch2011-08-252-9/+9
* | vbo: remove unused var, remove unneeded local varBrian Paul2011-08-241-4/+1
* | swrast: Remove swrast eject/validate texture image code.Brian Paul2011-08-241-79/+0
* | radeon: Fix flushing before writing a teximage's BO when !t->bo.Eric Anholt2011-08-241-12/+12
* | st/mesa: remove st_texture_image::face,level fieldsBrian Paul2011-08-244-23/+17
* | intel: use new gl_texture_image:Face, Level fieldsBrian Paul2011-08-249-51/+34
* | mesa: add gl_texture_image::Face, Level fieldsBrian Paul2011-08-242-0/+5
* | x11: add missing comma to fix compilationBrian Paul2011-08-241-1/+1
* | i965: Only map the necessary buffer range in brw_prepare_indicesIan Romanick2011-08-231-3/+2
* | tnl: Only map the necessary buffer range in bind_indicesIan Romanick2011-08-231-5/+21
* | mesa: Only map the necessary buffer range in vbo_get_minmax_indexIan Romanick2011-08-231-4/+19
* | mesa: Eliminate dd_function_table::MapBufferIan Romanick2011-08-2324-267/+123
* | radeon: Hack up an implementation of MapBufferRangeIan Romanick2011-08-231-0/+33
* | mesa: Fix incorrect access parameter passed to MapBufferIan Romanick2011-08-232-6/+2
* | mesa: Remove target parameter from dd_function_table::FlushMappedBufferRangeIan Romanick2011-08-235-8/+6
* | intel: Correctly check for read-only mappings in intel_bufferobj_map_rangeIan Romanick2011-08-231-1/+3
* | mesa: Remove target parameter from dd_function_table::MapBufferRangeIan Romanick2011-08-236-11/+7
* | mesa: Remove target parameter from dd_function_table::GetBufferSubDataIan Romanick2011-08-237-10/+6
* | mesa: Remove target parameter from dd_function_table::BufferSubDataIan Romanick2011-08-236-8/+5
* | mesa: Remove target parameter from dd_function_table::MapBufferIan Romanick2011-08-2324-69/+40
* | mesa: Remove target parameter from dd_function_table::UnmapBufferIan Romanick2011-08-2326-75/+53
* | i965: Fix typo in 2b224d66a01f3ce867fb05558b25749705bbfe7aEric Anholt2011-08-231-1/+1
* | i965/gen6+: Use non-normalized coordinates for GL_TEXTURE_RECTANGLE.Eric Anholt2011-08-234-2/+19
* | i965: Implement textureSize (TXS) on Gen4.Kenneth Graunke2011-08-233-6/+23
* | i965/fs: Implement textureSize (TXS) on Gen5+.Kenneth Graunke2011-08-236-10/+35
* | i965/fs: Rudimentary support for non-floating point texture results.Kenneth Graunke2011-08-231-1/+1
* | glsl: Add a new ir_txs (textureSize) opcode to ir_texture.Kenneth Graunke2011-08-233-1/+7
* | mesa: call _mesa_set_vp_override in glDrawTex*Chia-I Wu2011-08-231-0/+4
* | intel: Abort when DRI2 separate stencil handshake failsChad Versace2011-08-221-0/+7
* | glsl_to_tgsi: Fix a few more struct vs. class warnings.Kenneth Graunke2011-08-211-5/+5
* | glsl_to_tgsi: emit a MAD(b, -a, b) for !a && bBryan Cain2011-08-201-0/+52
* | glsl_to_tgsi: fix typoBryan Cain2011-08-201-1/+1
* | glsl_to_tgsi: implement ir_binop_all_equal using DP4 w/SGEBryan Cain2011-08-201-1/+19
* | glsl_to_tgsi: implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLTBryan Cain2011-08-201-2/+23
* | glsl_to_tgsi: implement ir_unop_any using DP4 w/saturate or DP4 w/SLTBryan Cain2011-08-201-4/+28
* | glsl_to_tgsi: make glsl_to_tgsi_visitor::emit_dp return the instructionBryan Cain2011-08-201-7/+7
* | glsl_to_tgsi: implement ir_binop_logic_or using an add w/saturate or add w/SLTBryan Cain2011-08-201-4/+27
* | glsl_to_tgsi: implement ir_unop_logic_not using 1-xBryan Cain2011-08-201-1/+11
* | android: build glslChia-I Wu2011-08-211-0/+32
* | android: build core mesaChia-I Wu2011-08-212-0/+214
* | mesa: android has no log2f nor ffsChia-I Wu2011-08-211-1/+7
* | mesa: fix !FEATURE_GL buildChia-I Wu2011-08-211-18/+18
* | i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.Kenneth Graunke2011-08-201-0/+3
* | i965/fs: Don't double-convert integer/boolean uniforms.Kenneth Graunke2011-08-191-16/+20