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* dri/radeon: nuke the remaining references to sareaEmil Velikov2014-08-213-11/+0
* dri/radeon: cleanup the radeon_context vtblEmil Velikov2014-08-218-163/+0
* dri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov2014-08-217-248/+2
* i965,meta: Stop unlocking the texture to try and prevent deadlocks.Kenneth Graunke2014-08-202-22/+0
* i965/vec4: Allow reswizzling writemasks when swizzle is single-valued.Matt Turner2014-08-201-27/+33
* i965: Flush the RC and TC before doing a fast clear resolveKristian Høgsberg2014-08-191-2/+2
* i965: Enable ARB_conditional_render_inverted on Gen6+.Chris Forbes2014-08-201-0/+1
* i965/vec4: Add a pass to reduce swizzles.Matt Turner2014-08-192-0/+99
* haiku/swrast: Add missing src include search path for missing util/macros.hAlexander von Gluck IV2014-08-191-0/+1
* i965/cfg: Add a foreach_block_and_inst_safe macro.Matt Turner2014-08-181-0/+4
* i965/cfg: Add a foreach_inst_in_block_safe macro.Matt Turner2014-08-181-0/+8
* i965/cfg: Add a foreach_block_safe macro.Matt Turner2014-08-181-0/+3
* i965: Pass a cfg pointer to generate_{code,assembly}.Matt Turner2014-08-1810-41/+39
* i965: Add and use foreach_block macro.Matt Turner2014-08-1814-143/+119
* i965/cfg: Embed link in bblock_t for main block list.Matt Turner2014-08-182-5/+7
* i965/fs: Optimize gl_FrontFacing calculation on Gen4/5.Matt Turner2014-08-181-5/+16
* i965/fs: Optimize gl_FrontFacing calculation on Gen6+.Matt Turner2014-08-181-6/+15
* i965: Use ~0 to represent true on Gen >= 6.Matt Turner2014-08-184-34/+102
* i965/fs: Optimize emit_bool_to_cond_code for logical exprs.Matt Turner2014-08-181-54/+87
* i965: Use UniformBooleanTrue value for boolean literal true.Matt Turner2014-08-182-2/+6
* i965: Remove dead call to _mesa_associate_uniform_storage().Matt Turner2014-08-181-6/+0
* i965: Enable instruction compaction on Gen8+.Matt Turner2014-08-181-1/+1
* i965: Add support for compacting 3-src instructions on Gen8.Matt Turner2014-08-181-0/+185
* i965: Add support for compacting 1- and 2-src instructions on Gen8.Matt Turner2014-08-181-13/+35
* i965/gen8: Add 3-src instruction compaction tables.Matt Turner2014-08-181-0/+27
* i965/gen8: Add instruction compaction tables.Matt Turner2014-08-181-0/+150
* i965: Update JIP/UIP compaction code to operate on bytes.Matt Turner2014-08-181-4/+8
* i965: Reverse condition ordering to let us support other gens.Matt Turner2014-08-181-3/+3
* i965/disasm: Add CSEL.Matt Turner2014-08-181-0/+1
* nouveau: don't keep stale pointer to free'd dataIlia Mirkin2014-08-161-0/+1
* nouveau: make sure to invalidate any vbo state as wellIlia Mirkin2014-08-161-0/+1
* i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hizJordan Justen2014-08-151-2/+4
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-152-3/+41
* i965/gen6: Force tile alignment for each stencil/hiz LODJordan Justen2014-08-151-3/+36
* i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODsJordan Justen2014-08-151-2/+19
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-157-17/+35
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-157-19/+73
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-153-59/+51
* i965/gen6 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2014-08-151-3/+3
* i965/gen6 blorp depth: calculate base surface width/heightJordan Justen2014-08-151-0/+13
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-152-0/+4
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-152-0/+6
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-152-0/+5
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-152-0/+50
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-154-1/+188
* i965/gen6: Adjust render height in errata case for MSAAJordan Justen2014-08-151-1/+17
* i965/gen6: Add support for layered renderbuffersJordan Justen2014-08-152-40/+43
* i965/gen6_surface_state.c: Remove (gen < 6) code pathJordan Justen2014-08-151-22/+0
* i965: Split gen6 renderbuffer surface state from gen5 and olderJordan Justen2014-08-154-0/+159
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