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* radeon: remove start/end offset + cleanup some whitespaceDave Airlie2008-12-225-62/+33
* radeon: fixup r500 FP emission for new CSDave Airlie2008-12-223-42/+95
* radeno: hopefully make r200/radeon buildDave Airlie2008-12-212-4/+6
* radeon: make DRI1 one work with new CS mechanismDave Airlie2008-12-0110-110/+187
* radeon: cs add print cs callbackJerome Glisse2008-11-161-1/+6
* radeon: fix pointer danglingJerome Glisse2008-11-166-12/+16
* radeon: update to libdrm-radeon API changesJerome Glisse2008-11-156-21/+23
* radeon: dri2 don't forget to free bufferJerome Glisse2008-11-143-1/+77
* r300: release bo from pixmapJerome Glisse2008-11-143-4/+26
* r300: convert to new relocations format (see libdrm-radeon)Jerome Glisse2008-11-147-49/+105
* r300: SetTex extension supportJerome Glisse2008-11-149-19/+113
* r300: cs + DRI2 supportJerome Glisse2008-11-1421-348/+958
* r300: bo and cs abstraction.Jerome Glisse2008-11-1436-3343/+3360
* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
* i965: Update WM maximum threads for G4X.Eric Anholt2008-11-121-2/+7
* i965: Add a big comment explaining my understanding of URB management.Eric Anholt2008-11-121-1/+38
* intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao2008-11-111-1/+3
* mesa: restore glapi/ prefix on #includeBrian Paul2008-11-101-1/+1
* GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul2008-11-101-17/+17
* dri: alloc __DRIscreen object with calloc()Brian Paul2008-11-101-1/+1
* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-061-4/+4
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-029-25/+24
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
* intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
* intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
* intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
* intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
* mesa: fix stand-alone glslcompiler buildBrian Paul2008-10-281-6/+2
* intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-2817-292/+272
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
* i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
* i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
* intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt2008-10-271-26/+17
* intel: GL_FALSE on a BO if it won't be modified when mapping this BO. (thanks...Xiang, Haihao2008-10-261-1/+1
* i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao2008-10-242-4/+12
* intel: fallback for intelEmitCopyBlit.Xiang, Haihao2008-10-241-10/+39
* i915: fix carsh in i830_emit_state. (bug #17766)Xiang, Haihao2008-10-211-1/+2
* fix span issue with really old ddx and non-tcl r100 chipsRoland Scheidegger2008-10-161-1/+1