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* intel: Avoid making tiled miptrees we won't be able to blit.Eric Anholt2013-04-081-14/+21
* intel: Do temporary CPU maps of textures that are too big to GTT map.Eric Anholt2013-04-081-0/+21
* intel: Add support for writing to our linear-temporary-CPU-map case.Eric Anholt2013-04-081-2/+23
* intel: Remove check for kernel 2.6.29.Kenneth Graunke2013-04-081-7/+0
* intel: Require kernel 2.6.39 for relaxed relocation support.Kenneth Graunke2013-04-082-5/+4
* i965: Remove a few BRW_STATE_... enum values.Kenneth Graunke2013-04-081-2/+0
* i965: Remove brw->vb.info and struct brw_vertex_info.Kenneth Graunke2013-04-082-13/+0
* i965: Remove the BRW_NEW_INPUT_DIMENSIONS flag.Kenneth Graunke2013-04-083-8/+0
* mesa: allow drivers not to expose ARB_color_buffer_float in GL core profileMarek Olšák2013-04-061-6/+12
* i965: Use a variable for the push constant size in kB.Kenneth Graunke2013-04-041-2/+3
* i965: Turn brw->urb.vs_size and gs_size into local variables.Kenneth Graunke2013-04-043-22/+12
* i965: Remove BRW_NEW_WM_INPUT_DIMENSIONS dirty bit.Kenneth Graunke2013-04-043-4/+0
* i965: Delete brw_vs_constval.c and the brw_wm_input_sizes atom.Kenneth Graunke2013-04-045-279/+0
* i965: Remove now dead brw_wm_prog_key::proj_attrib_mask field.Kenneth Graunke2013-04-043-29/+0
* i965: Remove fixed-function texture projection avoidance optimization.Kenneth Graunke2013-04-041-25/+18
* i965: Use ctx->Stencil._WriteEnabled in DEPTH_STENCIL_STATE.Kenneth Graunke2013-04-041-5/+1
* i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.Kenneth Graunke2013-04-041-1/+1
* i965: Ask the register allocator to round-robin through registers.Eric Anholt2013-04-041-0/+2
* i965: Reduce code duplication in handling of depth, stencil, and HiZ.Paul Berry2013-04-025-151/+178
* i965/fs: Allow CSE on pre-gen7 varying-index uniform loadsEric Anholt2013-04-011-1/+1
* i965/fs: Use LD messages for pre-gen7 varying-index uniform loadsEric Anholt2013-04-014-67/+84
* i965/fs: Don't double-emit SEND dependency workarounds at control flow.Eric Anholt2013-04-011-0/+2
* i965/fs: Bake regs_written into the IR instead of recomputing it later.Eric Anholt2013-04-017-33/+27
* i965/fs: Clean up the setup of gen4 simd16 message destinations.Eric Anholt2013-04-011-5/+4
* i965/fs: Do CSE on gen7's varying-index pull constant loads.Eric Anholt2013-04-011-11/+32
* i965/fs: Improve performance of varying-index uniform loads on IVB.Eric Anholt2013-04-012-18/+38
* i965/fs: Avoid inappropriate optimization with regs_written > 1.Eric Anholt2013-04-011-0/+6
* i965: Make the fragment shader pull constants index by dwords, not vec4s.Eric Anholt2013-04-016-16/+19
* i965: Make the constant surface interface take a normal byte size.Eric Anholt2013-04-014-17/+16
* i965/fs: Move varying uniform offset compuation into the helper func.Eric Anholt2013-04-013-11/+13
* i965/fs: Remove creation of a MOV instruction that's never used.Eric Anholt2013-04-011-1/+0
* i965/fs: Allow constant propagation into MACH.Eric Anholt2013-04-011-2/+4
* i965/fs: Fix bad interaction between tex swizzles and textureQueryLOD.Matt Turner2013-04-011-1/+1
* i965: Remove the old brw_optimize() code.Eric Anholt2013-04-013-120/+0
* i965/vs: Add a pass to set dependency control fields on instructions.Eric Anholt2013-04-013-0/+126
* i965: Dump shader source for linked shader programs.Eric Anholt2013-04-011-2/+18
* drirc: set always_have_depth_buffer for TopogonBrian Paul2013-04-011-0/+6
* i965: enable ARB_texture_storage_multisample on Gen6+Chris Forbes2013-03-311-0/+1
* i965: Fix an inconsistency inb the VUE map with gl_ClipVertex on gen4/5.Eric Anholt2013-03-301-7/+11
* intel: Remove a never-taken debug print path.Eric Anholt2013-03-301-5/+0
* i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards.Kenneth Graunke2013-03-295-6/+16
* i965: Add names for all instructions to dump_instruction() in FS and VS.Eric Anholt2013-03-294-25/+113
* i965: Enable ARB_texture_query_lod.Matt Turner2013-03-291-1/+3
* i965/fs: Generate LOD sampler message from ir_lod.Matt Turner2013-03-295-1/+20
* i965/fs: Use measured Gen7 instruction timings on Gen6.Matt Turner2013-03-291-1/+4
* i965/fs: Increase and document MAD latency on Gen7.Matt Turner2013-03-291-4/+18
* i965/fs: Add LRP instruction latency.Matt Turner2013-03-291-0/+26
* i965/fs: Add Haswell cycle timingsMatt Turner2013-03-291-9/+9
* i965: Note that write-after-write dependencies are blocking.Matt Turner2013-03-291-1/+1
* i965: Reword comment about the shared mathbox.Matt Turner2013-03-291-4/+4
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