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* nir: remove dependency on glslRob Clark2015-10-1610-9/+12
* glsl: move half<->float convertion to utilRob Clark2015-10-161-0/+1
* i965/vec4: Use the right number of UBOsIago Toral Quiroga2015-10-161-1/+1
* i965/fs: use the right number of UBOsIago Toral Quiroga2015-10-161-1/+1
* i965: android: add the i965_compile_FILES sources to the driverMauro Rossi2015-10-151-0/+1
* program: convert _mesa_init_gl_program() to take struct gl_program *Emil Velikov2015-10-157-19/+21
* i965: add arrays of arrays support for varyingsTimothy Arceri2015-10-152-5/+3
* i965: Don't hardcode FS in "validation failed!" message.Kenneth Graunke2015-10-141-1/+1
* i965/fs: Ignore compute shaders in brw_nir_lower_inputsJordan Justen2015-10-141-0/+4
* i965/fs: Simplify FS in brw_nir_lower_inputs to only support scalar modeJordan Justen2015-10-141-1/+2
* i965: Adapt SSBOs to work with their own separate index spaceIago Toral Quiroga2015-10-145-69/+71
* mesa: Rename {Num}UniformBlocks to {Num}BufferInterfaceBlocksIago Toral Quiroga2015-10-142-7/+7
* nir: split SSBO min/max atomic instrinsics into signed/unsigned versionsIago Toral Quiroga2015-10-142-21/+21
* i965/vec4: fix indentation in vec4_visitor::calculate_live_intervalsIago Toral Quiroga2015-10-141-8/+8
* i965/fs: Fix indentation in fs_live_variables::compute_start_endIago Toral Quiroga2015-10-141-9/+8
* i965/vs: Simplify fs_visitor's ATTR file.Kenneth Graunke2015-10-123-21/+49
* i965: Fix unsafe pointer when dumping VS/FS IRIago Toral Quiroga2015-10-122-2/+2
* i965/vec4: Implement b2f and b2i using negation.Matt Turner2015-10-111-7/+1
* i965/gs: Make MAX_GS_INPUT_VERTICES a #define in brw_context.h.Kenneth Graunke2015-10-103-4/+2
* i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.Kenneth Graunke2015-10-102-52/+42
* i965/vs: Fix a subtlety in the nr_attributes == 0 workaround.Kenneth Graunke2015-10-101-5/+7
* i965/vs: Unify URB entry size/read length calculations between backends.Kenneth Graunke2015-10-104-30/+38
* i965/cfg: Fix cfg_t::dump() when a block has no immediate dominator.Kenneth Graunke2015-10-101-1/+5
* i965/gen8: Remove gen<8 checks in gen8 codeChad Versace2015-10-091-4/+4
* i965/gen9: Enable rep clears on gen9Chad Versace2015-10-092-1/+6
* i965/gen9: Disable MCS for 1x color surfacesChad Versace2015-10-091-0/+8
* program: remove _mesa_init_*_program wrappersMarek Olšák2015-10-097-16/+13
* i965: Use _mesa_is_image_unit_valid() instead of gl_image_unit::_Valid.Francisco Jerez2015-10-093-6/+10
* i965: Don't tell the hardware about our UAV access.Francisco Jerez2015-10-096-19/+41
* i965/fs: Handle non-const sample number in interpolateAtSampleNeil Roberts2015-10-094-43/+130
* i965: Add a second successor to BRW_OPCODE_WHILENeil Roberts2015-10-091-0/+4
* mesa,meta: move gl_texture_object::TargetIndex initializationsBrian Paul2015-10-081-1/+4
* i965: Link compiler unit tests to libi965_compiler.laKristian Høgsberg Kristensen2015-10-081-6/+2
* i965: Break out backend compiler to its own libraryKristian Høgsberg Kristensen2015-10-082-77/+81
* i965/cs: Get max_cs_threads from brw_compiler devinfoKristian Høgsberg Kristensen2015-10-081-2/+3
* i965: Move brw_get_shader_time_index() call out of emit functionsKristian Høgsberg Kristensen2015-10-0811-31/+40
* i965: Move brw_select_clip_planes() to brw_shader.cppKristian Høgsberg Kristensen2015-10-082-25/+26
* i965: Use util_next_power_of_two() for brw_get_scratch_size()Kristian Høgsberg Kristensen2015-10-082-13/+6
* i965: Move brw_mark_surface_used() to brw_shader.cppKristian Høgsberg Kristensen2015-10-082-10/+10
* i965/cs: Split out helper for building local id payloadKristian Høgsberg Kristensen2015-10-084-78/+77
* i965: Move brw_link_shader() and friends to new file brw_link.cppKristian Høgsberg Kristensen2015-10-084-249/+284
* i965: Configure bufmgr debug options from intel_screen.cKristian Høgsberg Kristensen2015-10-083-17/+15
* util: Move DRI parse_debug_string() to utilKristian Høgsberg Kristensen2015-10-086-47/+11
* i965: Move brw_dump_ir() out of brw_*_emit() functionsKristian Høgsberg Kristensen2015-10-087-23/+12
* i965/gs/gen6: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-10-081-12/+18
* i965: Define FIRST_SPILL_MRF and FIRST_PULL_LOAD_MRF only once and in one placeIago Toral Quiroga2015-10-084-7/+6
* i965: make pull constant loads in gen6 start at MRFs 16/17Iago Toral Quiroga2015-10-082-3/+6
* i965: Fix remove_duplicate_mrf_writes so it can handle 24 MRFs in gen6Iago Toral Quiroga2015-10-081-1/+1
* radeon/r200: remove unneeded #include of colormac.hMark Janes2015-10-0611-11/+0
* i965: remove unneeded #include of colormac.hMark Janes2015-10-062-2/+0
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