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* i965/fs: Move varying uniform offset compuation into the helper func.Eric Anholt2013-04-013-11/+13
* i965/fs: Remove creation of a MOV instruction that's never used.Eric Anholt2013-04-011-1/+0
* i965/fs: Allow constant propagation into MACH.Eric Anholt2013-04-011-2/+4
* i965/fs: Fix bad interaction between tex swizzles and textureQueryLOD.Matt Turner2013-04-011-1/+1
* i965: Remove the old brw_optimize() code.Eric Anholt2013-04-013-120/+0
* i965/vs: Add a pass to set dependency control fields on instructions.Eric Anholt2013-04-013-0/+126
* i965: Dump shader source for linked shader programs.Eric Anholt2013-04-011-2/+18
* drirc: set always_have_depth_buffer for TopogonBrian Paul2013-04-011-0/+6
* i965: enable ARB_texture_storage_multisample on Gen6+Chris Forbes2013-03-311-0/+1
* i965: Fix an inconsistency inb the VUE map with gl_ClipVertex on gen4/5.Eric Anholt2013-03-301-7/+11
* intel: Remove a never-taken debug print path.Eric Anholt2013-03-301-5/+0
* i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards.Kenneth Graunke2013-03-295-6/+16
* i965: Add names for all instructions to dump_instruction() in FS and VS.Eric Anholt2013-03-294-25/+113
* i965: Enable ARB_texture_query_lod.Matt Turner2013-03-291-1/+3
* i965/fs: Generate LOD sampler message from ir_lod.Matt Turner2013-03-295-1/+20
* i965/fs: Use measured Gen7 instruction timings on Gen6.Matt Turner2013-03-291-1/+4
* i965/fs: Increase and document MAD latency on Gen7.Matt Turner2013-03-291-4/+18
* i965/fs: Add LRP instruction latency.Matt Turner2013-03-291-0/+26
* i965/fs: Add Haswell cycle timingsMatt Turner2013-03-291-9/+9
* i965: Note that write-after-write dependencies are blocking.Matt Turner2013-03-291-1/+1
* i965: Reword comment about the shared mathbox.Matt Turner2013-03-291-4/+4
* mesa: provide default implementation of QuerySamplesForFormatChris Forbes2013-03-291-1/+2
* i965: Tidy shader time printing code by using printf's field widths.Kenneth Graunke2013-03-281-12/+4
* i965/vs: Include URB payload setup in shader_time.Eric Anholt2013-03-282-4/+11
* i965/vs: Use a send from a 2-register VGRF for shader time writes.Eric Anholt2013-03-282-14/+13
* i965/vs: Teach copy propagation about sends from GRFs.Eric Anholt2013-03-283-7/+29
* i965/vs: Prepare split_virtual_grfs() for the presence of SENDs from GRFs.Eric Anholt2013-03-282-20/+45
* i965/fs: Include everything but the final FB write in shader_time.Eric Anholt2013-03-282-5/+15
* i965/fs: Switch shader_time writes to using GRFs.Eric Anholt2013-03-286-19/+63
* i965: Provide more detailed information to match shader_time to programs.Eric Anholt2013-03-281-13/+50
* i965: Track ARB program state along with GLSL state for shader_time.Eric Anholt2013-03-286-29/+47
* i965/fs: Improve performance of copy propagation dataflow using bitsets.Eric Anholt2013-03-281-33/+34
* android: fix Android.mk bug in mesa/drivers/dri/commonAdrian Marius Negreanu2013-03-251-1/+2
* i965: Shrink brw_vue_map struct.Paul Berry2013-03-242-2/+10
* i965/fs: Rename vp_outputs_written to input_slots_valid.Paul Berry2013-03-243-7/+7
* i965: Use brw.vue_map_geom_out instead of VS output VUE map where appropriate.Paul Berry2013-03-247-31/+29
* i965: Store the geometry output VUE map in brw_context.Paul Berry2013-03-243-0/+17
* i965: Move brw_vs_prog_data::outputs_written into VUE map.Paul Berry2013-03-247-21/+27
* i965/gen7: Use WE_all mode when enabling channel masks for URB write.Paul Berry2013-03-241-0/+1
* i965: Rename BRW_VARYING_SLOT_MAX -> BRW_VARYING_SLOT_COUNT.Paul Berry2013-03-245-10/+10
* i965: Clarify nomenclature: vert_result -> varyingPaul Berry2013-03-2315-152/+149
* i965: bump MAX_DEPTH_TEXTURE_SAMPLES to 4/8Chris Forbes2013-03-241-2/+2
* mesa: allow internalformat_query with multisample texture targetsChris Forbes2013-03-241-2/+4
* i965: Add a driconf option to disable flush throttling.Paul Berry2013-03-214-2/+15
* meta: fix incorrect slice, r coordinate computationBrian Paul2013-03-211-4/+9
* meta: minor indentation fixBrian Paul2013-03-211-1/+1
* i965/vs: Add IR dumping for immediates.Kenneth Graunke2013-03-201-0/+16
* i965: Don't use texture swizzling to force alpha to 1.0 if unnecessary.Kenneth Graunke2013-03-201-1/+2
* i965: Don't print a fatal-looking message if intelCreateContext fails.Kenneth Graunke2013-03-201-1/+0
* i965/gen7: Align all depth miplevels to 8 in the X direction.Eric Anholt2013-03-201-1/+9