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* i965/nir/vec4: Implement nir_intrinsic_ssbo_atomic_*Iago Toral Quiroga2015-09-252-0/+79
* i965/nir/fs: Implement nir_intrinsic_ssbo_atomic_*Iago Toral Quiroga2015-09-252-0/+79
* i965/nir/vec4: Implement nir_intrinsic_load_ssboIago Toral Quiroga2015-09-251-0/+54
* i965/nir/fs: Implement nir_intrinsic_load_ssboIago Toral Quiroga2015-09-251-0/+62
* i965/nir/vec4: Implement nir_intrinsic_store_ssboIago Toral Quiroga2015-09-251-0/+148
* i965/nir/fs: Implement nir_intrinsic_store_ssboIago Toral Quiroga2015-09-251-0/+71
* i965/vec4: Import surface message builder functions.Francisco Jerez2015-09-252-0/+273
* i965/vec4: Import helpers to convert vectors into arrays and back.Francisco Jerez2015-09-253-0/+130
* i965/vec4: Introduce VEC4 IR builder.Francisco Jerez2015-09-252-0/+603
* i965/wm: surfaces should have the API buffer size, not the drm buffer sizeSamuel Iglesias Gonsalvez2015-09-251-2/+2
* i965/wm: emit null buffer surfaces when null buffers are attachedSamuel Iglesias Gonsalvez2015-09-251-18/+26
* i965/fs/nir: implement nir_intrinsic_get_buffer_sizeSamuel Iglesias Gonsalvez2015-09-251-0/+24
* i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-255-0/+55
* i965/vec4/nir: implement nir_intrinsic_get_buffer_sizeSamuel Iglesias Gonsalvez2015-09-251-0/+26
* i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-255-0/+44
* glsl: Add parser/compiler support for unsized array's length()Samuel Iglesias Gonsalvez2015-09-252-0/+10
* i965/fs: Do not split buffer variablesIago Toral Quiroga2015-09-251-0/+1
* i965: handle visiting of ir_var_shader_storage variablesIago Toral Quiroga2015-09-251-2/+3
* i965: Upload Shader Storage Buffer Object surfacesIago Toral Quiroga2015-09-252-13/+57
* i965: Set MaxShaderStorageBuffers for compute shadersIago Toral Quiroga2015-09-251-0/+3
* i965: set ARB_shader_storage_buffer_object related constant valuesSamuel Iglesias Gonsalvez2015-09-251-0/+12
* i965: Implement DriverFlags.NewShaderStorageBufferIago Toral Quiroga2015-09-252-0/+3
* i965: Use 64-byte offset alignment for shader storage buffersIago Toral Quiroga2015-09-251-0/+9
* i965/cs: Implement DispatchComputeIndirect supportJordan Justen2015-09-243-4/+60
* i965/vec4: check swizzle before discarding a uniform on a 3src operandAlejandro Piñeiro2015-09-241-3/+6
* i965: Respect stride and subreg_offset for ATTR registersKristian Høgsberg Kristensen2015-09-241-1/+4
* mesa: rework Driver.CopyImageSubData() and related codeBrian Paul2015-09-243-31/+154
* i965: add ARB_texture_barrier supportIlia Mirkin2015-09-232-0/+10
* i965/gs: Fix extra level of indentation left by the previous commit.Kenneth Graunke2015-09-232-115/+111
* i965/gs: Use new NIR intrinsics.Kenneth Graunke2015-09-234-26/+48
* i915: Make hw_prim[] constVille Syrjälä2015-09-231-1/+1
* mesa: Remove unused HAVE_TRI_STRIP_1 definesIan Romanick2015-09-235-5/+0
* t_dd_dmatmp: Remove HAVE_QUADS supportIan Romanick2015-09-232-2/+0
* t_dd_dmatmp: Remove HAVE_QUAD_STRIPS supportIan Romanick2015-09-232-2/+0
* t_dd_dmatmp: Make "count" actually be the countIan Romanick2015-09-232-2/+2
* i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask neededAntia Puentes2015-09-232-3/+12
* i965/vec4: Detect and delete useless MOVs.Matt Turner2015-09-221-0/+22
* i965/vec4: Add support for fdph_replicatedJason Ekstrand2015-09-221-0/+5
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
* i965/vec4: refactor brw_vec4_copy_propagation.Alejandro Piñeiro2015-09-221-14/+18
* i965: fix textureGrad for cubemapsTapani Pälli2015-09-221-19/+182
* i965: Clean up GLSL compiler option setupJason Ekstrand2015-09-211-26/+20
* i965/skl: Use larger URB size where available.Ben Widawsky2015-09-211-1/+2
* i965: Fix MRF register number assertions for compr4.Kenneth Graunke2015-09-211-2/+2
* i965/vec4: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+6
* i965/fs: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+7
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-218-28/+28
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-214-7/+16
* i965: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-09-214-2/+10
* i965/vec4/nir: Remove all "this->" snippetsEduardo Lima Mitev2015-09-201-16/+15
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