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* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-1310-95/+96
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-134-19/+23
* i965: Reorganize brw_reg fields.Matt Turner2015-11-131-8/+8
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-1314-178/+185
* i965: Delete type field from backend_reg.Matt Turner2015-11-131-1/+0
* i965: Delete abs/negate fields from backend_reg.Matt Turner2015-11-133-5/+2
* i965: Make backend_reg inherit from brw_reg.Matt Turner2015-11-131-3/+3
* i965/fs: Replace nested ternary with if ladder.Matt Turner2015-11-131-6/+7
* mesa: In helpers, only check driver capability for metaNanley Chery2015-11-122-0/+12
* i965: Check instructions appear only on supported hardware.Matt Turner2015-11-121-0/+254
* i965: Add initial assembly validation pass.Matt Turner2015-11-125-0/+174
* i965: Add annotation_insert_error() and support for printing errors.Matt Turner2015-11-122-7/+71
* i965: Combine assembly annotations if possible.Matt Turner2015-11-121-5/+18
* i965: Set annotation_info's mem_ctx.Matt Turner2015-11-123-2/+5
* i965: Don't consider control flow instructions to have sources.Matt Turner2015-11-121-8/+8
* i965: Fill out instruction list.Matt Turner2015-11-123-14/+42
* i965: Consolidate is_3src() functions.Matt Turner2015-11-123-8/+7
* i965/fs/nir: fix the number of register written by FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsálvez2015-11-121-2/+14
* i965/skl/gt4: Fix URB programming restriction.Ben Widawsky2015-11-111-0/+9
* i965: Split nir_emit_intrinsic by stage with a general fallback.Kenneth Graunke2015-11-112-277/+381
* i965/brw_reg: Add a brw_VxH_indirect helperJason Ekstrand2015-11-111-0/+11
* i965: Print force_writemask_all in dump_instructions().Kenneth Graunke2015-11-112-0/+6
* i965: Combine BRW_NEW_*_BINDING_TABLE dirty bits.Kenneth Graunke2015-11-115-26/+14
* i965: Map GL_PATCHES to 3DPRIM_PATCHLIST_n.Kenneth Graunke2015-11-112-1/+10
* i965/nir/opt_peephole_ffma: Bypass fusion if any operand of fadd and fmul is ...Eduardo Lima Mitev2015-11-101-0/+31
* nir/nir_opt_peephole_ffma: Move this lowering pass to the i965 driverEduardo Lima Mitev2015-11-104-1/+272
* glsl: Lower UBO and SSBO access in glsl linkerKristian Høgsberg Kristensen2015-11-102-2/+2
* glsl: Drop exec_list argument to lower_ubo_referenceKristian Høgsberg Kristensen2015-11-101-1/+1
* i965/fs: Use regs_read/written for post-RA scheduling in calculate_depsJason Ekstrand2015-11-071-11/+4
* i965/nir/fs: Add comment for no-op memory barrier functionsFrancisco Jerez2015-11-061-0/+19
* i965/nir/fs: Implement new barrier functions for compute shadersJordan Justen2015-11-061-0/+7
* i965: Fix scalar VS float[] and vec2[] output arrays.Kenneth Graunke2015-11-054-2/+17
* i965/fs: Do not mark used surfaces in FS_OPCODE_GET_BUFFER_SIZEIago Toral Quiroga2015-11-052-4/+4
* i965/vec4: Do not mark used surfaces in VS_OPCODE_GET_BUFFER_SIZEIago Toral Quiroga2015-11-052-5/+5
* i965/vec4: Do not mark used direct surfaces in VS_OPCODE_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-053-13/+8
* i965/fs: Do not mark used direct surfaces in UNIFORM_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-052-11/+1
* i965/fs: Do not mark direct used surfaces in VARYING_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-053-13/+8
* i965/skl+: Enable support for 16x multisamplingNeil Roberts2015-11-052-1/+10
* mesa/meta: Use interpolateAtOffset for 16x MSAA copy blitNeil Roberts2015-11-051-2/+37
* meta/blit: Always try to enable GL_ARB_sample_shadingNeil Roberts2015-11-051-14/+2
* meta: Support 16x MSAA in the multisample scaled blit shaderNeil Roberts2015-11-053-10/+35
* i965/meta: Support 16x MSAA in the meta stencil blitNeil Roberts2015-11-051-5/+17
* i965/fs/skl+: Fix calculating gl_SampleID for 16x MSAANeil Roberts2015-11-051-1/+7
* i965: Support allocating the MCS buffer for 16x MSAANeil Roberts2015-11-051-0/+6
* i965: Support calculating the bits needed to set up 16x MSAANeil Roberts2015-11-051-1/+1
* i965/fs: Add a sampler program key for whether the texture is 16x MSAANeil Roberts2015-11-053-1/+16
* i965/vec4/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-053-2/+18
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-056-5/+60
* i965: Program 16x MSAA sample positions.Neil Roberts2015-11-053-7/+34
* i965: Handle 16x MSAA in IMS dimension munging code.Kenneth Graunke2015-11-051-2/+6
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