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* intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-051-0/+2
| | | | | This was causing hangs in cairogears, as we would blit to the 8bpp target (A8 texture) as 16bpp, and stomp over state objects.
* i965: fix 3DPRIMITIVE batch decode of the vertex count field.Eric Anholt2009-03-051-1/+1
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* i965: Stop dumping programs after the first all-zeroes entry.Eric Anholt2009-03-051-0/+8
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* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-056-1/+25
| | | | | This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller batchbuffers.
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-057-2/+42
| | | | | I keep wanting to hack this knob in as a one-time thing, so it seemed useful to have all the time.
* i965: Add a note about why the _NEW_STENCIL is required in draw_buffers.Eric Anholt2009-03-051-0/+5
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* intel: Remove a gratuitous MI_FLUSH after clearing with a blit.Eric Anholt2009-03-051-1/+0
| | | | | The 3D destination shares the same cache so we don't have any trouble with the later commands needing the writes flushed inside of the same batchbuffer.
* i965: Remove dead flushing code.Eric Anholt2009-03-054-23/+0
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* i965: comments and formatting fixesBrian Paul2009-03-051-4/+14
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* i965: fix emit_math1() function used for scalar instructionsBrian Paul2009-03-051-9/+32
| | | | | | | | | Instructions such as RCP, RSQ, LOG must smear the result of the function across the dest register's X, Y, Z and W channels (subject to write masking). Before this change, only the X component was getting written. Among other things, this fixes cube map texture sampling in GLSL shaders (since cube lookups involve normalizing the texcoord).
* i965: fix screen depth test in intel_validate_framebuffer)_Brian Paul2009-03-051-1/+2
| | | | front_region may be null.
* i965: init dest reg CondMask = COND_TR (the proper default)Brian Paul2009-03-051-2/+2
| | | | Plus fix up a debug printf.
* i965: add software fallback for conformant 3D textures and GL_CLAMPRobert Ellison2009-03-044-10/+40
| | | | | | | | | | | | | | | | | The i965 hardware cannot do GL_CLAMP behavior on textures; an earlier commit forced a software fallback if strict conformance was required (i.e. the INTEL_STRICT_CONFORMANCE environment variable was set) and 2D textures were used, but it was somewhat flawed - it could trigger the software fallback even if 2D textures weren't enabled, as long as one texture unit was enabled. This fixes that, and adds software fallback for GL_CLAMP behavior with 1D and 3D textures. It also adds support for a particular setting of the INTEL_STRICT_CONFORMANCE environment variable, which forces software fallbacks to be taken *all* the time. This is helpful with debugging. The value is: export INTEL_STRICT_CONFORMANCE=2
* mesa: call _mesa_get_cpu_string() to get CPU info for GL_RENDERER stringBrian Paul2009-03-041-66/+8
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* mesa: use Stencil._Enabled field instead of Stencil.EnabledBrian Paul2009-03-0216-19/+19
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* mesa: remove unused AUX buffersBrian Paul2009-03-021-4/+1
| | | | | | Remove all references to aux buffers 1..3. Keep AUX0 around for now just in case, but it'll probably go too someday. I don't know of any OpenGL drivers since the IRIX days that support aux color buffers.
* mesa: rename, reorder FRAG_RESULT_x tokensBrian Paul2009-02-288-15/+15
| | | | | | | s/FRAG_RESULT_DEPR/FRAG_RESULT_DEPTH/ s/FRAG_RESULT_COLR/FRAG_RESULT/COLOR/ Remove FRAG_RESULT_COLH (NV half-precision) output since we never used it. Next, we might merge the COLOR and DATA outputs (COLOR0, COLOR1, etc).
* intel: remove some unneeded buffer unmap callsBrian Paul2009-02-271-14/+2
| | | | Core mesa now unmaps the buffers if needed in these cases.
* i915: Add support for a new G33-like chipset.Shaohua Li2009-02-272-2/+13
| | | | | Signed-off-by: Shaohua Li <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* i965: texture fixes: bordered textures, fallback renderingRobert Ellison2009-02-271-3/+31
| | | | | | | | | | | | | | | | | | | | i965 doesn't natively support GL_CLAMP; it treats it like GL_CLAMP_TO_EDGE, which fails conformance tests. This fix adds a clause to the check_fallbacks() test to check whether GL_CLAMP is in use on any enabled 2D texture. If so, and if strict conformance is required (via INTEL_STRICT_CONFORMANCE), a software fallback is mandated. In addition, validate textures *before* checking for fallbacks, rather than after; otherwise, the texture state is never validated and can't be trusted. (In particular, if texturing is enabled and the sampler would access any level beyond level 0 of a texture, the sampler will segfault, because texture validation sets the firstLevel and lastLevel fields of a texture object so that the valid levels will be mapped and accessed correctly. If texture validation doesn't occur, only level 0 is accessed correctly, and that only because firstLevel and lastLevel happen to be set to 0.)
* intel: no-op the intel_finish_render_texture() functionBrian Paul2009-02-261-13/+10
| | | | It doesn't have to do anything. See comments for more details.
* intel: check texture formats in intel_validate_framebuffer()Brian Paul2009-02-261-0/+29
| | | | | | | | | We can't render into any texture format; only certain formats. Check that render-to-texture's format is renderable in the intel_validate_framebuffer() There seems to be a bug somewhere that causes rendering to rgb565 textures to be corrupted so disallow that for now. This will be revisted.
* intel: updated comment, some debug code (disabled)Brian Paul2009-02-261-3/+12
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* i965: rename draw_regions -> color_regionsroot2009-02-264-20/+20
| | | | Be a little more specific about what these are.
* i965: add missing init for region->widthBrian Paul2009-02-261-1/+2
| | | | | This doesn't seem to really effect anything but seeing width=0 in drawing regions was confusing.
* mesa: replace old prog_instruction::Sampler field with Aux fieldBrian Paul2009-02-263-10/+9
| | | | | | The i965 driver needs an extra instruction field for color output information. It was using the Sampler field for this. Use the Aux field instead. This will probaby be revisited at some point...
* i965: whitespace/indentation fixesBrian Paul2009-02-261-28/+24
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* intel: Revert disable of accelerated Bitmap, which slipped in with spans stuff.Eric Anholt2009-02-261-2/+2
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* i965: fix for RHW workaroundXiang, Haihao2009-02-262-43/+99
| | | | | | It is possible that an object whose vertices all are outside of a view plane is passed to clip thread due to the RHW workaround. This object should be rejected by clip thread. Fix bug #19879
* intel: Disable creating DRI2 FBconfigs with depth size != color size.Eric Anholt2009-02-261-1/+22
| | | | | | | | | | While it's a nice idea to be able to allow clients to choose a smaller (or bigger for 16bpp screens!) depth size, right now DRI2 hands back a buffer with a size that matches the drawable, rather than being based off of the visual. This led to problems in readback as parts of the driver disagreed on what format the depth buffer was really in. Fixes the remainder of bug #19447.
* intel: Add span code for z24 without stencil.Eric Anholt2009-02-261-2/+22
| | | | | | | | It seems that in this case the Mesa code is handing us x8z24 values instead of z24s8 values, so we need to not do the rotation. Fixes half of OGLconform depthrange.c. Bug #19447.
* intel: make template wrappers for the spans templates.Eric Anholt2009-02-254-189/+165
| | | | | This is insanity, but so is copying the same blocks containing the actual interesting code in the file three times each for the different tile formats.
* intel: Fix up x8r8g8b8 renderbuffer format so that alpha=1 spans code happens.Eric Anholt2009-02-252-1/+17
| | | | | | | | I was lured into a false sense of security by the fact that the spans code was already there, and a bunch of tests didn't catch the problem. oglconform's mask.c did, though. Bug #19970.
* i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt2009-02-256-13/+14
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* R300: Add support for RS600 chipsAlex Deucher2009-02-252-2/+12
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* i965: fix line stipple fallback for GL_LINE_STRIP primitivesRobert Ellison2009-02-231-1/+1
| | | | | | | | | | When doing line stipple, the stipple count resets on each line segment, unless the primitive is a GL_LINE_LOOP or a GL_LINE_STRIP. The existing code correctly identifies the need for a software fallback to handle conformant line stipple on GL_LINE_LOOP primitives, but neglects to make the same assessment on GL_LINE_STRIP primitives. This fixes it so they match.
* texmem: fix typo from brianp's changes.Dave Airlie2009-02-221-1/+1
| | | | Reported by cjb via tinderbox on irc
* mesa: use an array for current texture objectsBrian Paul2009-02-215-18/+18
| | | | Use loops to consolidate lots of texture object code.
* mesa: re-org texgen stateBrian Paul2009-02-212-31/+35
| | | | New gl_texgen struct allows quite a bit of code reduction.
* intel: Fix intelSetTexBuffer miptree leak.Kristian Høgsberg2009-02-211-2/+7
| | | | The intelImage also holds a reference to the miptree, so unref that as well.
* intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.Eric Anholt2009-02-217-13/+27
| | | | | | | | | | This lets us avoid allocing new buffers for renderbuffers, finalized miptrees, and PBO-uploaded textures when there's an unreferenced but still active one cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded textures. The size of BOs allocated for a desktop running current GL cairogears on i915 is cut in half with this. Note that this means we require libdrm 2.4.5.
* i965: Fix render target read domains.Eric Anholt2009-02-211-2/+1
| | | | | | | | | | | We were asking for something illegal (write_domain != 0 && read_domains != write_domain) because at the time of writing the region surfaces were used for texturing occasionally as well, and we weren't really clear on the model GEM was going to use. This reliably triggered a kernel bug with domain handling, resulting in oglconform mustpass.c failure. Of course, it only became visible after 01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing.
* i965: use the new prog_instruction::TexShadow fieldBrian Paul2009-02-205-6/+11
| | | | | GLSL shadow() sampler calls are properly propogated down to the driver now. The glean glsl1 shadow() tests work (except for the alpha channel).
* i965: check depth_mode in translate_tex_format() for MESA_FORMAT_S8_Z24Brian Paul2009-02-201-1/+9
| | | | | Note that I24X8 vs. A24X8 vs. L24X8 doesn't seem to make any difference for texture/shadow compare, however.
* i965: separate emit_op() and emit_tex_op() functionsBrian Paul2009-02-201-50/+63
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* i965: update comment, use const qualifierBrian Paul2009-02-201-4/+2
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* i965: var renaming, clean-upBrian Paul2009-02-201-13/+11
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* i965: added commentBrian Paul2009-02-201-1/+1
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* intel: fix datatype typo, s/GLboolean/GLuint/Brian Paul2009-02-201-1/+1
| | | | Fixes mysterious failures in glean glsl1 test.
* i965: additional debug outputBrian Paul2009-02-201-0/+8
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