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Commit message (
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Author
Age
Files
Lines
*
i965/gen4-5: Stop using bogus polygon_offset_scale field.
Eric Anholt
2013-06-26
3
-20
/
+1
*
i915: Use the current drawbuffer's depth for polygon offset scale.
Eric Anholt
2013-06-26
1
-1
/
+1
*
intel: Add perf debug for glCopyPixels() fallback checks.
Eric Anholt
2013-06-26
1
-33
/
+39
*
i965: Add debug to INTEL_DEBUG=blorp describing hiz/blit/clear ops.
Eric Anholt
2013-06-26
3
-0
/
+39
*
i965/fs: Dump IR when fatally not compiling due to bad register spilling.
Eric Anholt
2013-06-26
1
-1
/
+2
*
xmlpool/build: Make sure to set mo properly
Naohiro Aota
2013-06-25
1
-1
/
+1
*
i965: Remove the rest of brw_update_draw_buffer().
Eric Anholt
2013-06-25
1
-27
/
+5
*
i965: Stop updating FBO state on drawbuffers change.
Eric Anholt
2013-06-25
1
-8
/
+0
*
i965: Stop recomputing drawbuffer bounds on drawbuffer change.
Eric Anholt
2013-06-25
1
-2
/
+0
*
i965: Remove _NEW_DEPTH state flagging on drawbuffers change.
Eric Anholt
2013-06-25
2
-3
/
+1
*
intel: Stop doing special _NEW_STENCIL state flagging on drawbuffers.
Eric Anholt
2013-06-25
4
-10
/
+5
*
i965: Stop flagging viewport/scissor change on drawbuffers change.
Eric Anholt
2013-06-25
1
-3
/
+0
*
i965: Stop flagging _NEW_POLYGON on drawbuffers change.
Eric Anholt
2013-06-25
1
-5
/
+0
*
radeon: Remove gratuitous custom framebuffer resize code.
Eric Anholt
2013-06-25
1
-31
/
+0
*
intel: Remove gratuitous custom framebuffer resize code.
Eric Anholt
2013-06-25
1
-30
/
+6
*
mesa: Remove the Initialized field from framebuffers.
Eric Anholt
2013-06-25
3
-6
/
+0
*
mesa: Remove Driver.GetBufferSize and its callers.
Eric Anholt
2013-06-25
2
-2
/
+0
*
mesa: Use shared code for converting shader targets to short strings.
Eric Anholt
2013-06-21
1
-5
/
+4
*
glsl: Remove ir_print_visitor.h includes and usage
Eric Anholt
2013-06-21
9
-11
/
+2
*
gen7: fix GPU hang on WebGL texture-size test
Jordan Justen
2013-06-18
1
-1
/
+1
*
intel: Remove unused IS_POWER_OF_TWO() macro.
Eric Anholt
2013-06-18
1
-2
/
+0
*
intel: Allow blorp CopyTexSubImage to nonzero destination slices.
Eric Anholt
2013-06-17
3
-14
/
+9
*
intel: Allow blit CopyTexSubImage to nonzero destination slices.
Eric Anholt
2013-06-17
1
-14
/
+9
*
intel: Directly implement blit glBlitFramebuffer instead of awkward reuse.
Eric Anholt
2013-06-17
3
-70
/
+72
*
intel: Move XRGB->ARGB blit logic into intel_miptree_blit().
Eric Anholt
2013-06-17
4
-100
/
+63
*
intel: Fix Y tiling support for glCopyTexSubImage's alpha override.
Eric Anholt
2013-06-17
1
-4
/
+4
*
intel: Make batch macros for doing BCS_SWCTRL setup.
Eric Anholt
2013-06-17
1
-37
/
+47
*
mesa: Hide weirdness of 1D_ARRAY textures from Driver.CopyTexSubImage().
Eric Anholt
2013-06-17
2
-6
/
+7
*
i965: Assume flexible hardware primitive restart exists in the future.
Kenneth Graunke
2013-06-14
1
-1
/
+1
*
i965: Shrink Gen5 VUE map layout to be the same as Gen4.
Chris Forbes
2013-06-16
6
-40
/
+7
*
i965: Implement 16-wide math on G45 and Ironlake.
Kenneth Graunke
2013-06-16
2
-0
/
+28
*
i965/gen7: Enable support for fast color clears.
Paul Berry
2013-06-12
1
-0
/
+20
*
i965/gen7+: Disable fast color clears on shared regions.
Paul Berry
2013-06-12
4
-0
/
+42
*
i965/gen7+: Resolve color buffers when necessary.
Paul Berry
2013-06-12
7
-3
/
+37
*
i965/gen7+: Ensure that front/back buffers are fast-clear resolved.
Paul Berry
2013-06-12
3
-12
/
+15
*
i965/blorp: Write blorp code to do render target resolves.
Paul Berry
2013-06-12
6
-0
/
+96
*
i965/blorp: Expand clear class hierarchy to prepare for RT resolves.
Paul Berry
2013-06-12
2
-25
/
+35
*
i965/gen7+: Implement fast color clear operation in BLORP.
Paul Berry
2013-06-12
9
-14
/
+240
*
i965/gen7+: Create helper functions for single-sample MCS buffers.
Paul Berry
2013-06-12
2
-0
/
+128
*
i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.
Paul Berry
2013-06-12
3
-5
/
+7
*
i965/gen7+: Create an enum for keeping track of fast color clear state.
Paul Berry
2013-06-12
6
-0
/
+104
*
intel: Conditionally compile mcs-related code for i965 only.
Paul Berry
2013-06-12
2
-1
/
+9
*
intel: Keep region name in intel_miptree_create_for_dri2_buffer().
Paul Berry
2013-06-12
1
-0
/
+1
*
i965: Emit the depth/stencil state pointer directly, not via atoms.
Kenneth Graunke
2013-06-11
7
-80
/
+18
*
i965: Emit the CC state pointer directly rather than via atoms.
Kenneth Graunke
2013-06-11
5
-30
/
+18
*
i965: Emit the BLEND_STATE pointer directly rather than via atoms.
Kenneth Graunke
2013-06-11
5
-30
/
+18
*
Revert "i965: Disable unused pipeline stages once at startup on Gen7+."
Kenneth Graunke
2013-06-11
3
-6
/
+13
*
i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies.
Eric Anholt
2013-06-10
1
-13
/
+37
*
i965/vs: Allow copy propagation into MUL/MACH.
Eric Anholt
2013-06-10
1
-2
/
+4
*
i965/vs: Use the MAD instruction when possible.
Eric Anholt
2013-06-10
4
-0
/
+43
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