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Commit message (Expand)AuthorAgeFilesLines
* r600: implement LOG op in compilerPierre Ossman2009-11-022-3/+214
* r600: implement EXP op in compilerPierre Ossman2009-11-022-3/+130
* radeon: add missing includeDave Airlie2009-10-311-0/+1
* radeon: use _mesa_get_current_tex_unitDave Airlie2009-10-311-1/+1
* intel: Use GTT mapping when available for swrast.Eric Anholt2009-10-303-1/+88
* intel: Fix up z24_x8 depth spans since the texformat merge.Eric Anholt2009-10-301-12/+6
* i965: Add an index assert on get_fp_inst array like other compiler arrays.Eric Anholt2009-10-301-0/+1
* i965: Fix BRW_WM_MAX_INSN to reflect current limits.Eric Anholt2009-10-301-2/+1
* intel: Set the texture format in the TFP path.Eric Anholt2009-10-301-3/+6
* r600: remove duplicate lineAlex Deucher2009-10-301-1/+0
* r600: fill in some missing tex formatsAlex Deucher2009-10-301-0/+46
* r600: fix a warning, update commentsAlex Deucher2009-10-301-3/+3
* r600: use AUTO_INDEX for draw - saves cmd buffer spaceAndre Maasikas2009-10-301-18/+10
* intel: fix up some XRGB breakageBrian Paul2009-10-303-3/+6
* intel: update intel_create_renderbuffer(format), add XRGB supportBrian Paul2009-10-2912-36/+57
* r600: remove the no rrb messagesAlex Deucher2009-10-291-2/+0
* r600: Add support for ARB_depth_clampAlex Deucher2009-10-292-2/+14
* intel: remove memcpy_get_tex_image() codeBrian Paul2009-10-291-103/+2
* i965: indentation fixBrian Paul2009-10-291-1/+1
* i965: make brw_sf_prog_key::sprite_origin_lower_left one bitBrian Paul2009-10-293-5/+5
* i965: make brw_wm_prog_key a little smallerBrian Paul2009-10-291-3/+3
* i915: Fix 1D texture mapping in the t coordinate.Eric Anholt2009-10-291-0/+6
* i915: Correct and make use of the defines for 32-bit depth texture modes.Eric Anholt2009-10-292-4/+9
* i965: avoid shader translation on window resizeBrian Paul2009-10-291-6/+11
* i965: define, use BRW_MAX_DRAW_BUFFERSBrian Paul2009-10-293-4/+8
* i965: remove unused varBrian Paul2009-10-291-1/+0
* i965: don't use context state in emit_fb_write()Brian Paul2009-10-293-2/+5
* i965: use macros to get/set prog_instruction::Aux fieldBrian Paul2009-10-294-8/+14
* i965: minor code reformattingBrian Paul2009-10-291-4/+3
* i915: Implement min/max LOD clamping with the hardware.Eric Anholt2009-10-294-40/+46
* i965: Replace a MIN(MAX()) with CLAMP().Eric Anholt2009-10-291-2/+2
* intel: check for single memcpy() in memcpy_get_tex_image()Brian Paul2009-10-291-5/+10
* i965: Fix fallout from ARB_depth_clamp enablement that broke glDepthRange.Eric Anholt2009-10-291-4/+10
* intel: Don't bother MI_FLUSHing on glFlush in the DRI2 case.Eric Anholt2009-10-291-1/+1
* intel: Clean up merge leftover from the DRI2 swap throttling.Eric Anholt2009-10-291-5/+0
* intel: remove debug codeBrian Paul2009-10-291-1/+0
* intel: added fast memcpy path for glGetTexImage()Brian Paul2009-10-291-3/+102
* radeon: fix incorrect Z format in radeon_alloc_renderbuffer_storage()Brian Paul2009-10-291-2/+2
* mesa: re-remove s3v and trident driver filesBrian Paul2009-10-283-1350/+0
* Merge branch 'texformat-rework'Brian Paul2009-10-2886-1225/+2378
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| * radeon: add case for MESA_FORMAT_X8_Z24 in radeon_create_renderbuffer()Brian Paul2009-10-271-1/+6
| * mesa: choose texture format in core mesa, not driversBrian Paul2009-10-258-32/+6
| * mesa: remove calls to _mesa_compressed_row_stride()Brian Paul2009-10-255-15/+15
| * mesa: remove _mesa_compressed_texture_size()Brian Paul2009-10-241-1/+1
| * mesa: change compressed texture size callsBrian Paul2009-10-244-31/+16
| * dri/drivers: update driNewRenderbuffer() to take a gl_formatBrian Paul2009-10-2220-145/+136
| * radeon: simplify radeon_create_renderbuffer()Brian Paul2009-10-223-29/+27
| * r600: fix depth span macros for format changesAlex Deucher2009-10-221-4/+4
| * radeon: fix some renderbuffer format bugsBrian Paul2009-10-222-7/+7
| * i915: replace MESA_FORMAT_Z24_S8 with MESA_FORMAT_S8_Z24Brian Paul2009-10-211-2/+2
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