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* i965/blorp: Make state setup C-safeJason Ekstrand2016-04-263-4/+4
| | | | | | | | Previously they (very rarely) used C++isms that prevented them from being compiled as C. As of this commit, they can be compiled as either C or C++. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Convert brw_blorp.cpp to a C fileJason Ekstrand2016-04-262-5/+2
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Make all of brw_blorp.h accessible to CJason Ekstrand2016-04-261-9/+8
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Turn brw_blorp_params into a C-style structJason Ekstrand2016-04-267-80/+71
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Turn coord_transform into a C-style structJason Ekstrand2016-04-262-17/+16
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Turn blorp_surface_info into a C-style structJason Ekstrand2016-04-267-69/+69
| | | | | | | | | | This commit is mostly mechanical except that it changes where we set the swizzle. Previously, the blorp_surface_info constructor defaulted the swizzle to SWIZZLE_XYZW. Now, we memset to zero and fill out the swizzle when we setup the rest of the struct. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Roll mip_info into surface_infoJason Ekstrand2016-04-262-37/+17
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Get rid of the blorp_blit_params classJason Ekstrand2016-04-262-167/+131
| | | | | | | It was really just a wrapper around the function that constructed it. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Remove the hiz params classJason Ekstrand2016-04-262-37/+42
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Remove the clear params classesJason Ekstrand2016-04-261-132/+83
| | | | | | | | | They didn't really add anything other than a key and extra layers of function calls. This commit just inlines the extra functions and gets rid of the extra classes. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Remove the arguments to brw_blorp_params()Jason Ekstrand2016-04-262-9/+5
| | | | | | | No one was using anything other than the defaults. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Refactor to get rid of the get_wm_prog virtual functionJason Ekstrand2016-04-267-97/+58
| | | | | | | | | | | | Instead of having a virtual member function for getting the WM/PS kernel, we simply add fields for prog_data and the kernel to brw_blorp_parms and always make sure those get set as part of the different constructors. v2: Use use prog_data != NULL to check for a valid program instead of a magic kernel offset value Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/meta: initialize values to avoid random behaviour on error pathJuha-Pekka Heikkila2016-04-261-1/+1
| | | | | | | | | if brw_meta_stencil_blit() errored at wrong place 'target' would be uninitialized and cause random behaviour on leaving the funtion. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: Remove every double semi-colonJakob Sinclair2016-04-261-1/+1
| | | | | | Signed-off-by: Jakob Sinclair <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Unroll SIMD16 DDY_FINE on Sandybridge.Kenneth Graunke2016-04-251-1/+5
| | | | | | | | | | | | This fixes 10 dEQP-GLES3 subtests: dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*. Matt noticed that our Piglit tests for this use even numbered registers, while the failing dEQP tests use odd numbered registers. We believe that it works for even numbered registers, but not otherwise. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Mark URB reads as volatile.Kenneth Graunke2016-04-251-0/+3
| | | | | | | | | | They can be affected by URB writes. In the upcoming scalar TCS backend, this prevents read-modify-write cycles from being broken by CSE removing reads. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Make a few tessellation related functions non-static.Kenneth Graunke2016-04-253-47/+51
| | | | | | | | Also, move them to brw_shader.cpp so they're in a location for code used by both the vec4 and fs worlds. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965/tex_image: Flush certain subnormal ASTC channel valuesNanley Chery2016-04-231-0/+87
| | | | | | | | | | | | | | | When uploading a linear, void-extent, ASTC LDR block on Skylake, we are required to flush to zero the UNORM16 channel values that would be denormalized. This is specifically required for the values: 1, 2, and 3. Fixes the 14 failing tests in: dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.* v2: Split out flushing function (Kristian Høgsberg) v3: Map with READ instead of INVALIDATE (Kenneth Graunke) Signed-off-by: Nanley Chery <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/blorp: Enable for buffer resolvesTopi Pohjolainen2016-04-231-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Enable for normal color clearsTopi Pohjolainen2016-04-231-0/+9
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+Topi Pohjolainen2016-04-231-7/+26
| | | | | | | | | | | | | This is equivalent of 73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2 for blorp. v2 (Ken): No need to call _mesa_format_has_color_component() now that the number of components is gotten from _mesa_base_format_component_count(). Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Do not trigger re-emission of base state addressTopi Pohjolainen2016-04-232-2/+0
| | | | | | | | In case blorp needs to configure it will be just as if render or compute pipeline had configured it. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Reconfigure base state address only if neededTopi Pohjolainen2016-04-233-3/+7
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bitsTopi Pohjolainen2016-04-232-5/+2
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-2362-46/+179
| | | | Reviewed-by: Topi Pohjolainen <[email protected]
* i965: Introduce state flag for blorpTopi Pohjolainen2016-04-232-0/+3
| | | | | | | | | | | | | | | | | | | | | | | In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger re-emission of the entire 3D pipeline on the next draw. However, there are some packets BLORP simply leaves alone, so there's no need to re-emit them. Trying to reduce the set of dirty bits flagged after BLORP runs is tricky. Instead, we introduce a BRW_NEW_BLORP flag. This should be set on any atom which emits a packet that BLORP also emits. When BLORP runs, it will flag BRW_NEW_BLORP, causing those packets to get re-emitted. This also makes it easy to avoid re-emitting specific atoms - we can simply drop the BRW_NEW_BLORP flag on those. To start, we assume that all packets need to be re-emitted. This is the safest approach and closest to the existing code's behavior. Many of these are obviously not required, and can be dropped in subsequent patches. Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965/blorp/gen6: Use normal base state address setupTopi Pohjolainen2016-04-233-54/+5
| | | | | | | | | | | | This is identical to the blorp version which only differs in case fragment shader isn't used. In that case blorp would reset batch buffer address to zero. This is not really needed, and having blorp to use base state address setup that is compatible with normal upload allows one to skip resetting it. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove pointers to non-existing atomsTopi Pohjolainen2016-04-231-8/+0
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable KHR_texture_compression_astc_hdr on Gen9Nanley Chery2016-04-222-4/+3
| | | | | | | | | | | | Although Gen9 samples from most HDR ASTC surfaces of correctly, there currently are no software workarounds to fix the incorrect sampling that occurs in others of certain color endpoint modes. With this change, we are no longer failing the 14 tests from: dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.* Signed-off-by: Nanley Chery <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Disable channel expressions for scalar GS, TCS, TES.Kenneth Graunke2016-04-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Broadwell, I get the following shader-db statistics: Tessellation Control Shaders: total instructions in shared programs: 57327 -> 57012 (-0.55%) instructions in affected programs: 27334 -> 27019 (-1.15%) helped: 45 HURT: 0 total cycles in shared programs: 265692 -> 255188 (-3.95%) cycles in affected programs: 263122 -> 252618 (-3.99%) helped: 184 HURT: 26 Tessellation Evaluation Shaders: total instructions in shared programs: 23236 -> 23157 (-0.34%) instructions in affected programs: 2791 -> 2712 (-2.83%) helped: 27 HURT: 0 total cycles in shared programs: 151858 -> 149704 (-1.42%) cycles in affected programs: 151858 -> 149704 (-1.42%) helped: 101 HURT: 114 Geometry Shaders: Orbital Explorer goes from 6442 -> 6356 instructions. Two Shadow of Mordor shaders increase by a single instruction. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Add support for 2x msaaTopi Pohjolainen2016-04-222-10/+9
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Add support for encoding/decoding interleaved 2x msaaTopi Pohjolainen2016-04-221-8/+36
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: don't lower mod() in glsl irSamuel Iglesias Gonsálvez2016-04-221-1/+0
| | | | | | | | | NIR will lower it in nir_opt_algebraic. No change in shader-db. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/surface_state: Use libisl functions for image format loweringJason Ekstrand2016-04-213-120/+12
| | | | | | | This lets us delete some redundant code and keep all of the image_load_store format lowering logic in one place: libisl. Reviewed-by: Chad Versace <[email protected]>
* i965/fs_surface_builder: Use isl instead of mesa for format infoJason Ekstrand2016-04-211-66/+52
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965/fs_surface_builder: Add a helper for converting GL to ISL formatsJason Ekstrand2016-04-211-0/+55
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinatesJason Ekstrand2016-04-211-0/+1
| | | | | | | | | Previously, we were relying on has_matching_typed_format returning true for MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning 1 for MESA_FORMAT_NONE. When we switch to ISL, this behaviour will no longer be something we can rely on. Reviewed-by: Chad Versace <[email protected]>
* i965/fs_surface_builder: Take a GL format enum instead of mesa_formatJason Ekstrand2016-04-213-9/+10
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Add a dependency on libislJason Ekstrand2016-04-211-1/+6
| | | | | | | To avoid build issues, ensure that you're running `make' at the top level and/or you've executed `make clean' beforehand. Reviewed-by: Chad Versace <[email protected]>
* i965: Always use Y-tiled buffers on SKL+Ben Widawsky2016-04-214-8/+30
| | | | | | | | | | | | | | | | Starting with Skylake, the display engine is capable of scanning out from Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency. This also has the added benefit of being able to fast clear the winsys buffer. Note that the buffer allocation done for mipmaps will already never allocate an X-tiled buffer for GEN9. This has an almost universal positive impact on benchmarks, some improving by as much as 20%. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix clear code for ignoring colormask for XRGB formats on Gen9+.Kenneth Graunke2016-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | In commit cda886a4851ab767fba40e8474d6fa8190347e4f, Neil made us stop advertising RGBX formats on Gen9+, as the hardware apparently no longer has working fast clear support for those formats. Instead, we just fall back to RGBA formats, and use SCS to override alpha to 1.0. This is fine, but had one unintended side effect: it made us fall back to slow clears when the color mask disables alpha. Normally, we ignore the color mask for non-existent channels. This includes alpha for XRGB formats as writing garbage to the X channel is harmless. But, now that we use RGBA, we think there's a real alpha channel, and can't do the optimization. To hack around this, check if _BaseFormat is GL_RGB and ignore alpha. Improves WebGL Aquarium performance on Skylake GT3e by about 50% by letting it use repclears instead of slow clears. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/blorp: Improve precission of blitting coordinates when clippingIago Toral Quiroga2016-04-211-61/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | We do this in two steps: first we clip the dst rect and adjust the src rect accordingly. Then we do it the other way around. In both passes the adjustment part involves multiplying by a scale factor that can lead to a small precision loss. This is breaking a few dEQP tests. Specifically, the problem happens when we need to clip the same coordinate twice. For example, if srcX0 and dstX0 need both to be clipped we want to avoid the situation where we clip srcX0 first, then adjust dstX0 accordingly but then we realize that the resulting dstX0 still needs to be clipped, so we clip dstX0 and adjust srcX0 again. Each of these two passes can lead to precission loss. What we want to do here is detect the rect that leads to the largest clip (accounting for the scale factor involved), clip that rect and adjust the other one. With this we ensure that the adjusted coordinate does not need to be clipped again and we can skip a second pass, improving precision. Fixes the following 4 dEQP tests: dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_linear Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Mark Janes <[email protected]>
* i965/fs: Readd opt_drop_redundant_mov_to_flags().Matt Turner2016-04-212-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b449366587b5f3f64c6fb45fe22c39e4bc8a4309. I removed the pass thinking that it was now not useful, but that was not true. I believe I ran shader-db on HSW and saw no results, but HSW does not use the unlit centroid workaround code and as a result does not emit redundant MOV_DISPATCH_TO_FLAGS instructions. On IVB, the shader-db results are: total instructions in shared programs: 6650806 -> 6646303 (-0.07%) instructions in affected programs: 106893 -> 102390 (-4.21%) helped: 793 total cycles in shared programs: 56195538 -> 56103720 (-0.16%) cycles in affected programs: 873048 -> 781230 (-10.52%) helped: 553 HURT: 209 On SNB, the shader-db results are: total instructions in shared programs: 7173074 -> 7168541 (-0.06%) instructions in affected programs: 119757 -> 115224 (-3.79%) helped: 799 total cycles in shared programs: 98128032 -> 98072938 (-0.06%) cycles in affected programs: 1437104 -> 1382010 (-3.83%) helped: 454 HURT: 237 Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/blorp: Do not emit pma stall on gen9+Topi Pohjolainen2016-04-211-1/+3
| | | | | | | This was left out from the original gen8 upload introduction. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: automake: remove gratuitous "+" during variable assignmentEmil Velikov2016-04-211-2/+2
| | | | | | | There is not initial assignment, thus appending to it does not work. Fixes: b27c85c4c08 "i965: add build rule for brw_nir_trig_workarounds.c" Signed-off-by: Emil Velikov <[email protected]>
* dri/common: add MESA_FORMAT_R8G8B8{A8, X8}_UNORM formats as supported configsRob Herring2016-04-211-0/+10
| | | | | | | | | Add MESA_FORMAT_R8G8B8A8_UNORM and MESA_FORMAT_R8G8B8X8_UNORM formats as these are the preferred formats for Android. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: add build rule for brw_nir_trig_workarounds.c on AndroidRob Herring2016-04-214-2/+49
| | | | | | | | | | | Commit bfd17c76c126 ("i965: Port INTEL_PRECISE_TRIG=1 to NIR.") added a generated file brw_nir_trig_workarounds.c which broke the Android build. Add the necessary makefiles to the Android build. Cc: Kenneth Graunke <[email protected]> Signed-off-by: Rob Herring <[email protected]> Tested-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/tiled_memcpy: don't unconditionally use __builtin_bswap32Jonathan Gray2016-04-211-1/+14
| | | | | | | | | | Use the defines Mesa configure sets to indicate presence of the bswap32 builtins. This lets i965 work on OpenBSD again after the changes that were made in 0a5d8d9af42fd77fce1492d55f958da97816961a. Signed-off-by: Jonathan Gray <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Reduce the urb size requirement for vertex bufferTopi Pohjolainen2016-04-211-5/+4
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Reduce the size of vertex bufferTopi Pohjolainen2016-04-211-12/+19
| | | | | | | | | | | Previously the vertex buffer consisted of eight floats per vertex of which six where constants. These can be as easily provided by vertex fetcher as it is capable of filling vertex elements with constant one and zero. This reduces the size of the vertex buffer from 3 * 8 * 4 = 96 to 3 * 2 * 4 = 24 bytes. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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