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authorJason Ekstrand <[email protected]>2016-04-16 13:25:24 -0700
committerJason Ekstrand <[email protected]>2016-04-21 20:44:27 -0700
commit541e6c05000b87cee02d5f8e1adc7973c2a2deea (patch)
tree1e7cb661c9248a66b03ba5ab313cd6c9754308f7 /src/mesa/drivers/dri
parente53cabe730ca5d4491a34fd1d385face3100f5bb (diff)
i965/surface_state: Use libisl functions for image format lowering
This lets us delete some redundant code and keep all of the image_load_store format lowering logic in one place: libisl. Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_surface_formats.c109
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c21
3 files changed, 12 insertions, 120 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 1d3d5b2a1fb..39c3d917413 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1579,8 +1579,6 @@ bool brw_render_target_supported(struct brw_context *brw,
bool brw_losslessly_compressible_format(const struct brw_context *brw,
uint32_t brw_format);
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
-mesa_format brw_lower_mesa_image_format(const struct brw_device_info *devinfo,
- mesa_format format);
/* brw_performance_monitor.c */
void brw_init_performance_monitors(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 7ff15ccc0c6..aa8a0a12fa5 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -942,112 +942,3 @@ brw_depth_format(struct brw_context *brw, mesa_format format)
unreachable("Unexpected depth format.");
}
}
-
-mesa_format
-brw_lower_mesa_image_format(const struct brw_device_info *devinfo,
- mesa_format format)
-{
- switch (format) {
- /* These are never lowered. Up to BDW we'll have to fall back to untyped
- * surface access for 128bpp formats.
- */
- case MESA_FORMAT_RGBA_UINT32:
- case MESA_FORMAT_RGBA_SINT32:
- case MESA_FORMAT_RGBA_FLOAT32:
- case MESA_FORMAT_R_UINT32:
- case MESA_FORMAT_R_SINT32:
- case MESA_FORMAT_R_FLOAT32:
- return format;
-
- /* From HSW to BDW the only 64bpp format supported for typed access is
- * RGBA_UINT16. IVB falls back to untyped.
- */
- case MESA_FORMAT_RGBA_UINT16:
- case MESA_FORMAT_RGBA_SINT16:
- case MESA_FORMAT_RGBA_FLOAT16:
- case MESA_FORMAT_RG_UINT32:
- case MESA_FORMAT_RG_SINT32:
- case MESA_FORMAT_RG_FLOAT32:
- return (devinfo->gen >= 9 ? format :
- devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RGBA_UINT16 : MESA_FORMAT_RG_UINT32);
-
- /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component
- * are supported. IVB doesn't support formats with more than one component
- * for typed access. For 8 and 16 bpp formats IVB relies on the
- * undocumented behavior that typed reads from R_UINT8 and R_UINT16
- * surfaces actually do a 32-bit misaligned read. The alternative would be
- * to use two surface state entries with different formats for each image,
- * one for reading (using R_UINT32) and another one for writing (using
- * R_UINT8 or R_UINT16), but that would complicate the shaders we generate
- * even more.
- */
- case MESA_FORMAT_RGBA_UINT8:
- case MESA_FORMAT_RGBA_SINT8:
- return (devinfo->gen >= 9 ? format :
- devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RGBA_UINT8 : MESA_FORMAT_R_UINT32);
-
- case MESA_FORMAT_RG_UINT16:
- case MESA_FORMAT_RG_SINT16:
- case MESA_FORMAT_RG_FLOAT16:
- return (devinfo->gen >= 9 ? format :
- devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RG_UINT16 : MESA_FORMAT_R_UINT32);
-
- case MESA_FORMAT_RG_UINT8:
- case MESA_FORMAT_RG_SINT8:
- return (devinfo->gen >= 9 ? format :
- devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RG_UINT8 : MESA_FORMAT_R_UINT16);
-
- case MESA_FORMAT_R_UINT16:
- case MESA_FORMAT_R_FLOAT16:
- case MESA_FORMAT_R_SINT16:
- return (devinfo->gen >= 9 ? format : MESA_FORMAT_R_UINT16);
-
- case MESA_FORMAT_R_UINT8:
- case MESA_FORMAT_R_SINT8:
- return (devinfo->gen >= 9 ? format : MESA_FORMAT_R_UINT8);
-
- /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported
- * by the hardware.
- */
- case MESA_FORMAT_R10G10B10A2_UINT:
- case MESA_FORMAT_R10G10B10A2_UNORM:
- case MESA_FORMAT_R11G11B10_FLOAT:
- return MESA_FORMAT_R_UINT32;
-
- /* No normalized fixed-point formats are supported by the hardware. */
- case MESA_FORMAT_RGBA_UNORM16:
- case MESA_FORMAT_RGBA_SNORM16:
- return (devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RGBA_UINT16 : MESA_FORMAT_RG_UINT32);
-
- case MESA_FORMAT_R8G8B8A8_UNORM:
- case MESA_FORMAT_R8G8B8A8_SNORM:
- return (devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RGBA_UINT8 : MESA_FORMAT_R_UINT32);
-
- case MESA_FORMAT_R16G16_UNORM:
- case MESA_FORMAT_R16G16_SNORM:
- return (devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RG_UINT16 : MESA_FORMAT_R_UINT32);
-
- case MESA_FORMAT_R8G8_UNORM:
- case MESA_FORMAT_R8G8_SNORM:
- return (devinfo->gen >= 8 || devinfo->is_haswell ?
- MESA_FORMAT_RG_UINT8 : MESA_FORMAT_R_UINT16);
-
- case MESA_FORMAT_R_UNORM16:
- case MESA_FORMAT_R_SNORM16:
- return MESA_FORMAT_R_UINT16;
-
- case MESA_FORMAT_R_UNORM8:
- case MESA_FORMAT_R_SNORM8:
- return MESA_FORMAT_R_UINT8;
-
- default:
- unreachable("Unknown image format");
- }
-}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 218afab6457..f88c43ba60f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -39,6 +39,8 @@
#include "program/prog_instruction.h"
#include "main/framebuffer.h"
+#include "isl/isl.h"
+
#include "intel_mipmap_tree.h"
#include "intel_batchbuffer.h"
#include "intel_tex.h"
@@ -1168,20 +1170,21 @@ const struct brw_tracked_state brw_cs_image_surfaces = {
static uint32_t
get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
{
+ const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ uint32_t hw_format = brw_format_for_mesa_format(format);
if (access == GL_WRITE_ONLY) {
- return brw_format_for_mesa_format(format);
- } else {
+ return hw_format;
+ } else if (isl_has_matching_typed_storage_image_format(devinfo, hw_format)) {
/* Typed surface reads support a very limited subset of the shader
* image formats. Translate it into the closest format the
* hardware supports.
*/
- if ((_mesa_get_format_bytes(format) >= 16 && brw->gen <= 8) ||
- (_mesa_get_format_bytes(format) >= 8 &&
- (brw->gen == 7 && !brw->is_haswell)))
- return BRW_SURFACEFORMAT_RAW;
- else
- return brw_format_for_mesa_format(
- brw_lower_mesa_image_format(brw->intelScreen->devinfo, format));
+ return isl_lower_storage_image_format(devinfo, hw_format);
+ } else {
+ /* The hardware doesn't actually support a typed format that we can use
+ * so we have to fall back to untyped read/write messages.
+ */
+ return BRW_SURFACEFORMAT_RAW;
}
}