aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/r300/r300_reg.h
Commit message (Collapse)AuthorAgeFilesLines
* [r300] Replace more magic number by register definitions from AMDChristoph Brill2008-02-251-0/+18
|
* [r300] clean some more magic registers based on AMD specChristoph Brill2008-02-251-0/+136
|
* [r300] Update some magic registers to real namesChristoph Brill2008-02-251-0/+11
|
* [r300] Document Z-buffer related register ZB_BW_CNTLChristoph Brill2008-02-251-0/+42
|
* [r300] document VAP_CNTL based on AMD specChristoph Brill2008-02-251-0/+26
|
* [r300] Document some of the wild guesses in VAP_OUTPUT_VTX_FMT based on AMD specChristoph Brill2008-02-251-7/+10
|
* [r300] document type 3 packets to draw primitives based on AMD specChristoph Brill2008-02-251-2/+40
|
* r300: fixup some more namesDave Airlie2008-02-231-16/+27
|
* r300: some initial register info from doc dropDave Airlie2008-02-231-2/+29
|
* Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL.Oliver McFadden2007-11-051-1/+6
|
* r300: initial user clipping for TCL pathsDave Airlie2007-11-051-0/+8
| | | | | I've no idea if this code might break something or how it should interact with vertex shaders, it makes the clip demo work for me
* r300: fix misnumber registerDave Airlie2007-11-031-1/+1
|
* Framework for supporting z24_s8 and z32 depth textures on r300.Ian Romanick2007-10-171-0/+8
|
* r300: Use the R300_PVS_UPLOAD_* defines.Oliver McFadden2007-07-161-0/+15
|
* r300: Added the clip plane upload defines.Oliver McFadden2007-07-161-0/+8
|
* r300: Vertex program position end bits are known.Oliver McFadden2007-06-241-3/+5
| | | | | Possibly performance may improve by setting it to the last instruction that writes result.position, rather than the last instruction in the vertex program.
* r300: Added a comment regarding the R300_VAP_CLIP registers.Oliver McFadden2007-06-071-0/+2
|
* r300: Explain the R300_VAP_OUTPUT_VTX_FMT_1 register.Oliver McFadden2007-06-071-0/+2
|
* r300: Document registers 0x2220 to 0x2230.Oliver McFadden2007-05-301-0/+10
| | | | These registers are per-pixel and per-vertex X and Y clipping planes.
* r300: Use the CP_PACKET3 macro for Type 3 packets.Oliver McFadden2007-05-301-0/+1
| | | | | | | | | I haven't converted all of the Type 3 packets to the CP_PACKET3 macro yet because some of the Type 3 packet defines are missing from the R300 register definition file. These defines need to be copied from DRM and Mesa into the R300 register definition file then copied into both DRM and Mesa.
* Revert "r300: Removed the R300_RS_INTERP_[0-9]_UNKNOWN (magic) defines."Oliver McFadden2007-05-271-0/+6
| | | | | | | | This reverts commit bb3558e6517209086cf8426bbe4743da50351158. This commit caused a regression reported by Markus Amsler <[email protected]>. Apparently these defines are required, although I'm not sure why.
* r300: Removed R300_PFS_NODE_LAST_NODE replaced by R300_PFS_NODE_OUTPUT_COLOR.Oliver McFadden2007-05-261-2/+0
|
* r300: Removed the R300_RS_INTERP_[0-9]_UNKNOWN (magic) defines.Oliver McFadden2007-05-231-6/+0
| | | | | Supposedly you need to set these values for the interpolaters to work, but they seem to work fine without these values.
* r300: Use the defined values when writing to R300_RS_ROUTE_0.Oliver McFadden2007-05-131-0/+5
|
* r300: A few very minor indenting corrections.Oliver McFadden2007-05-131-4/+4
|
* r300; Indent would destroy r300_reg.h, so add *INDENT-OFF*.Oliver McFadden2007-05-091-0/+3
|
* r300: Added R300_PRIM_NUM_VERTICES_MASK suggested by Jerome Glisse.Oliver McFadden2007-05-091-0/+1
|
* r300: Added R300_AA_DISABLE for R300_GB_AA_CONFIG.Oliver McFadden2007-05-061-0/+1
|
* r300: don't enable VAP/TCL on cards that don't support itDave Airlie2007-04-101-0/+1
|
* r300: No assertion when accessing incomplete texture images.Nicolai Haehnle2007-03-241-4/+5
| | | | | | | There used to be an assertion when a fragment program accesses an incomplete texture image. Work around this assertion. Note: I am unsure whether this workaround produces the desired result (0,0,0,1) on all hardware.
* r300: Fix fragment program instruction pairing and register allocationNicolai Haehnle2007-03-191-1/+3
| | | | | | | | | | | | | There were a number of bugs related to the pairing of vector and scalar operations where swizzles ended up using the wrong source register, or an instruction was moved forward and ended up overwriting an aliased register. The new algorithm for register allocation is quite conservative and may run out of registers before necessary. On the plus side, It Just Works. Pairing is done whenever possible, and in more cases than before, so in practice this change should be a net win.
* r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden2007-03-131-4/+4
| | | | enough information is known about them to be sure as to what the values mean.
* Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden2007-03-131-0/+2
| | | | | | Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these values are really unknown; ideally more reverse engineering should be done to determine what these values mean and when they should be set.
* Documented the value written for R300_TX_CNTL cache flush.Oliver McFadden2007-03-131-0/+1
|
* Guess another unknown register used for R300 pacification.Oliver McFadden2007-03-131-0/+4
|
* Guess another unknown register in R300 command buffer initialization. ↵Aapo Tahkola2007-03-111-0/+1
| | | | (Oliver McFadden)
* r300: Use register name & add a register about shading.Christoph Bill2007-03-011-0/+4
|
* r300: Use reg definition when available & add missing reg definition.Christoph Bill2007-03-011-1/+7
|
* Add early register descritpion.Christoph Bill2007-03-011-0/+4
| | | | | | This need more work on case where we can disable or enable early (stencil, alpha might need it to be disable).
* Add CMPH instruction to fragprogJerome Glisse2006-11-011-0/+2
| | | | | CMPH a0, a1, a2 -> if a2 > 0.5 return a1 else return a0 Guessed by examinating LIT instruction handling of FGLRX.
* Removing some of r200 dependency, cleaning up code a bit,Jerome Glisse2006-09-121-27/+42
| | | | | | | and fixing a couple of warning. More cleanup and shuffle to come. I have tested this change they might broke things especialy with r300_texstate.c change (format_x doesn't seems to be use at all by r300).
* Add R300_VAP_CNTL 0x2140 and cosmetic cleanup.Jerome Glisse2006-07-041-395/+498
|
* Fix typo.Jerome Glisse2006-06-291-1/+1
|
* Fog support (Ewald Snel)Aapo Tahkola2006-04-111-1/+15
|
* implement arl and enable hw nv_vp.Aapo Tahkola2006-03-221-0/+2
|
* Fix broken max mipmap leveling that was horribly wrong.Aapo Tahkola2006-03-131-4/+4
|
* Add all pci ids known by ddx to radeon dri driver. Remove the entries not ↵Roland Scheidegger2006-02-251-0/+1
| | | | known by ddx (probably secondary ids, non-existant cards and similar). Add rs400 to the family enum, and configure the rv410 like a 2 quad chip (?)
* per vp sw fallbacksAapo Tahkola2006-01-271-0/+2
|
* Sync from drm.Aapo Tahkola2006-01-201-0/+28
|
* Missing patch from Ben Skeggs:Aapo Tahkola2006-01-091-1/+7
| | | | | | | | | | | | | | | | | | | | | | Lots of changes, and fixes for some badness on my behalf. 1. Disposable data used during fp compile is now per-context, rather than per-program to save memory. 2. Track usage of INPUT/TEMP registers from Mesa program, free them when no longer required so the hw temps can be re-used. 3. Changed LAST_NODE to OUTPUT_COLOR (see r300_reg.h) 4. Implemented remaining ARB_f_p instructions, with the exception of the trig/LIT opcodes. 5. Treat ZERO/ONE swizzles the same way as other native swizzles. 6. emit_arith changes, basically a complete re-write. Should produce cleaner instructions, but no real functional changes. internal reg -> hw reg routines shared with emit_tex. A bit messy still.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 04:47:30 +0000