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path: root/src/mesa/drivers/dri/intel
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* intel: add support for using API_OPENGL_COREJordan Justen2012-07-301-1/+1
* i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.Paul Berry2012-07-271-1/+1
* intel: Make more consistent use of _mesa_is_{user,winsys}_fbo()Paul Berry2012-07-266-8/+12
* i965/msaa: Switch on 8x MSAA for Gen7.Paul Berry2012-07-241-2/+4
* i965/msaa: Adjust MCS buffer allocation for 8x MSAA.Paul Berry2012-07-241-2/+25
* intel: move error on create context to proper pathJordan Justen2012-07-241-1/+1
* mesa: move some format helper functions to glformats.cBrian Paul2012-07-241-1/+1
* i965: Add a driconf option to disable GL_ARB_blend_func_extended.Kenneth Graunke2012-07-192-2/+3
* intel: Add a comment explaining why we early return on matching BO names.Eric Anholt2012-07-171-0/+4
* intel: Drop other checks for old loader version.Eric Anholt2012-07-171-38/+26
* intel: Replace the non-getBuffersWithFormat compat path with an error message.Eric Anholt2012-07-172-21/+8
* intel: Remove dead intel_framebuffer_has_hiz().Eric Anholt2012-07-172-13/+0
* intel: Convert to using private depth/stencil buffers (v2)Eric Anholt2012-07-173-652/+39
* intel: Add a function for creating a private window system buffer.Eric Anholt2012-07-172-2/+20
* intel: Fix build broken by ETC1 patchChad Versace2012-07-161-0/+12
* intel: Enable GL_OES_compressed_ETC1_RGB8_textureChad Versace2012-07-163-1/+73
* gbm: Add new gbm_bo_import entry pointKristian Høgsberg2012-07-161-1/+7
* intel: Don't call _mesa_get_format_bytes for MESA_FORMAT_NONEKristian Høgsberg2012-07-161-1/+4
* i965: Use the blitter in intel_bufferobj_subdata for busy BOs on Gen6+.Kenneth Graunke2012-07-121-16/+10
* i965/msaa: Enable CMS layout on Gen7 for the formats that support it.Paul Berry2012-07-111-1/+18
* i965/msaa: Allocate MCS buffer when CMS MSAA is in use.Paul Berry2012-07-113-0/+69
* i965/msaa: Add an enum to describe MSAA layout.Paul Berry2012-07-114-42/+78
* intel: Implement __DRIimage::createSubImage and bump supported version to 5Kristian Høgsberg2012-07-113-3/+50
* intel: Add offset field to miptreeKristian Høgsberg2012-07-113-3/+11
* intel: Add support for new __DRIimage formatsKristian Høgsberg2012-07-111-0/+15
* i965: Revert the VBOs-in-system-memory hack.Eric Anholt2012-07-111-8/+5
* i965: Add hardware context support.Kenneth Graunke2012-07-102-2/+9
* intel: Share common __DRIimage allocation codeKristian Høgsberg2012-07-051-40/+19
* intel: Just look up image->internal_format using _mesa_get_format_base_formatKristian Høgsberg2012-07-051-10/+2
* intel: Remove unused __DRIimage::data_type fieldKristian Høgsberg2012-07-052-13/+0
* intel: Fix a comment typo.Eric Anholt2012-07-041-1/+1
* i965: enable ARB_instanced_arrays extensionJordan Justen2012-06-271-0/+1
* i965: Enable the GL_ARB_shader_bit_encode extension.Kenneth Graunke2012-06-071-0/+1
* mesa: consolidate internal glCopyTexSubImage1/2/3D codeBrian Paul2012-06-061-29/+11
* mesa: consolidate internal glTexSubImage1/2/3D codeBrian Paul2012-06-061-13/+15
* mesa: consolidate internal glTexImage1/2/3D codeBrian Paul2012-06-061-53/+7
* intel: Change vendor string to "Intel Open Source Technology Center".Kenneth Graunke2012-06-011-1/+1
* i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2012-05-251-1/+5
* i965/msaa: Properly handle sliced layout for Gen7.Paul Berry2012-05-254-55/+134
* i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.Paul Berry2012-05-251-5/+40
* i965: Gut the separate OpenGL ES extension enabling.Kenneth Graunke2012-05-233-144/+4
* i965: create code path to handle primitive restart in hardwareJordan Justen2012-05-231-0/+4
* i965/gen6+: Add support for GL_ARB_blend_func_extended.Eric Anholt2012-05-231-0/+1
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-0/+5
* i965: Drop a layer of indirection in doing HiZ resolves.Eric Anholt2012-05-232-39/+9
* i965: Replace intel_need_resolve with the hiz ops it maps to.Eric Anholt2012-05-233-17/+21
* i965: Add an interface for doing hiz ops from C code.Eric Anholt2012-05-232-0/+32
* intel: Fork the intel_clear.c file between i915 and i965.Eric Anholt2012-05-231-203/+0
* i965: Completely annotate the batch bo when aub dumping.Paul Berry2012-05-222-1/+5
* intel: When AUB dumping, flush before emitting final bitmap command.Paul Berry2012-05-221-1/+3
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