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path: root/src/mesa/drivers/dri/intel/intel_screen.c
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* i915: Add an option for testing the effect of early Z in classic mode.Eric Anholt2009-06-091-1/+5
| | | | | | The early Z stuff is supposed to be unsafe without some more work in the enable/disable path (in particular, how do we want to get it disabled on the way out to the X Server?), but at the moment is 6% in OA.
* intel: remove extra \n from warning stringBrian Paul2009-06-091-1/+1
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* intel: Add support for tiled textures.Eric Anholt2009-06-041-1/+12
| | | | | | | | | | This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now.
* i965: send all warnings through _mesa_warning()Robert Ellison2009-05-141-1/+1
| | | | | | | | | | | One warning message: drm_i915_getparam: -22 was still being sent to fprintf(). This causes all Piglit tests to fail, even with MESA_DEBUG=0. Using _mesa_warning() to emit the message allows the general Mesa controls for messages like this to be applied.
* i965: Use GTT maps when available to upload vertex arrays and system VBOs.Eric Anholt2009-04-061-0/+6
| | | | | | | This speeds up OA on my GM45 by 21% (more than the original CPU cost of the upload path). We might still be able to squeeze a few more percent out by avoiding repeatedly mapping/unmapping buffers as we upload elements into them.
* intel: Clean up some a leftover from sedding of bufmgr context->screen move.Eric Anholt2009-04-061-3/+0
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* Fix DRI2 accelerated EXT_texture_from_pixmap with GL_RGB format.Eric Anholt2009-03-201-0/+1
| | | | | | | | | | | | | | This requires upgrading the interface so that the argument to glXBindTexImageEXT isn't just dropped on the floor. Note that this only fixes the accelerated path on Intel, as Mesa's texture format support is missing x8r8g8b8 support (right now, GL_RGB textures get uploaded as a8r8gb8, but in this case we're not doing the upload so we can't really work around it that way). Fixes bugs with compositors trying to use shaders that use alpha channels, on windows without a valid alpha channel. Bug #19910 and likely others as well. Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove last of _mesa_unreference_framebuffer() callsBrian Paul2009-03-071-1/+1
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* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-051-1/+2
| | | | | This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller batchbuffers.
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-051-1/+2
| | | | | I keep wanting to hack this knob in as a one-time thing, so it seemed useful to have all the time.
* intel: Disable creating DRI2 FBconfigs with depth size != color size.Eric Anholt2009-02-261-1/+22
| | | | | | | | | | While it's a nice idea to be able to allow clients to choose a smaller (or bigger for 16bpp screens!) depth size, right now DRI2 hands back a buffer with a size that matches the drawable, rather than being based off of the visual. This led to problems in readback as parts of the driver disagreed on what format the depth buffer was really in. Fixes the remainder of bug #19447.
* intel: Fix up x8r8g8b8 renderbuffer format so that alpha=1 spans code happens.Eric Anholt2009-02-251-1/+8
| | | | | | | | I was lured into a false sense of security by the fact that the spans code was already there, and a bunch of tests didn't catch the problem. oglconform's mask.c did, though. Bug #19970.
* intel: Clean up several 965 memory leaks on context destroy.Eric Anholt2009-02-171-0/+1
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* intel: Add x8r8g8b8 visuals to DRI1 fbconfigs alongside a8r8gb8.Eric Anholt2009-02-101-25/+35
| | | | | This involved fixing driConcatConfigs to not return const (which had made a mess of a previous patch too).
* gallium: Fixups for driCreateConfigs MSAA support.Michel Dänzer2009-02-101-0/+4
| | | | Add the MSAA samples array or make sure its contents are initialized.
* re-add MSAA supportBrian Paul2009-02-091-3/+8
| | | | | | | | | (cherry picked from commit f7d80aa00611917bc8ce637136d982b151b8f44f) This also involved adding the new MSAA fields to driCreateConfigs(). Also, re-add prog_instructions->Sampler field for i965 driver. Will have to revisit that.
* intel: Correct FBconfig color masks with DRI2. Fail at copy and paste.Eric Anholt2009-01-311-2/+2
| | | | | This still leaves us with a broken depth 32 visual, but now it's the server's visual setup that's at fault.
* intel: Expose more FBconfigs in the 3D driver.Eric Anholt2009-01-301-2/+52
| | | | | | We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8) on either class of chipsets. The only restriction is no mixing bpp when also mixing tiling. This shouldn't be occurring currently.
* intel: #include clean-upsBrian Paul2009-01-261-11/+9
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* intel: make intelUpdateScreenFromSAREA() staticBrian Paul2009-01-261-1/+1
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* intel: remove unused varBrian Paul2009-01-261-2/+0
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* intel: move intelInitExtensions() and related code into new intel_extensions.cBrian Paul2009-01-261-0/+1
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* intel: Move swap-related functions from intel_buffers.c to new ↵Brian Paul2009-01-261-0/+1
| | | | intel_swapbuffers.c
* [intel] Go back to using the typedef for the sarea structmesa_7_3_rc3Timo Aaltonen2009-01-201-4/+4
| | | | | | The upstream linux kernel headers and libdrm kernel headers disagree on the tag name for the sarea struct: _drm_i915_sarea vs drm_i915_sarea. They both typedef it to drm_i915_sarea_t though, so just use that.
* Remove third buffer support from Mesa.Dave Airlie2008-12-231-15/+0
| | | | This is part of the deprecated pageflipping infrastructure.
* intel: restore old vertex submit paths for i8xx hardware.Dave Airlie2008-12-021-0/+1
| | | | | | | Intel docs state that only 830/845 have VBOs, 855/865 don't. So lets just not use them on i8xx at all. This restores the old pre-vbo code and uses it on all 8xx hw.
* mesa: standardize on C99's uint*_t instead of u_int*_tKeith Whitwell2008-09-211-2/+2
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* mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul2008-09-181-6/+6
| | | | Makefile.template
* intel: Destroy bufmgr in screen destroy, not context.Eric Anholt2008-09-161-0/+1
| | | | | | | Caused server crashes on second context creation since 7e0bbdcf033981282978554c2e68ce48b55aa291. Bug #17600.
* intel: Remove dead allow_batchbuffer param.Eric Anholt2008-09-121-5/+0
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* intel: track move of bo_exec from drivers to bufmgr.Eric Anholt2008-09-101-1/+0
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* intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt2008-09-101-38/+9
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* intel: Move the bufmgr back to the screen.Eric Anholt2008-09-101-0/+98
| | | | | | | Mesa requires that we be able to share objects between contexts, which means that the objects need to be created by the same bufmgr, and the bufmgr internally requires pthread protection for thread safety. Rely on the bufmgr having appropriate locking.
* DRI2: Drop sarea, implement swap buffers in the X server.Kristian Høgsberg2008-08-291-114/+2
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* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-241-100/+15
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-241-15/+100
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* Merge branch 'drm-gem'Eric Anholt2008-08-081-100/+15
|\ | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_span.c src/mesa/main/fbobject.c This converts the i915 driver to use the GEM interfaces for object management.
| * drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-111-122/+11
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| * intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-021-13/+26
| | | | | | | | | | | | | | | | | | The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
| * intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt2008-07-011-1/+8
| | | | | | | | | | | | It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
| * Merge commit 'origin/master' into drm-gemEric Anholt2008-06-181-1/+10
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| * | [gem] Enable bo_reuse by default.Eric Anholt2008-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | The objects are swappable, so we're less concerned by excessive object allocation now, and it's about a 20% performance improvement. If we get concerns about the memory consumption from others, we can look into a compromise position later.
| * | [intel] Convert drivers to using libdrm bufmgr code.Eric Anholt2008-06-031-1/+1
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| * | [intel-GEM] Add tiling support to swrast.Keith Packard2008-05-061-6/+12
| | | | | | | | | | | | | | | Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
| * | Dump buffer tiled status from intelPrintSAREAKeith Packard2008-05-051-6/+6
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| * | [intel] Fix build for GEM. TTM is now disabled, and fencing is gone.Eric Anholt2008-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | Fencing was used in two places: ensuring that we didn't get too many frames ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on buffers like we would do for CPU access on them. The "don't get too far ahead" is now the responsibility of the execution manager (kernel).
* | | intel: sync to vblank by defaultJesse Barnes2008-07-311-1/+1
| | | | | | | | | | | | | | | | | | Effectively default to vblank_mode=3 on Intel to avoid tearing by default. Users wanting to go "as fast as possible" (despite not being able to see frames faster than their refresh rate allows) can still set the vblank_mode manually.
* | | Revert "intel: disable zero-copy TFP."Dave Airlie2008-07-251-4/+0
| | | | | | | | | | | | | | | | | | This reverts commit 94979950e8991bd44899eb4067c3ae43449ce51e. I've fixed it instead
* | | intel: disable zero-copy TFP.Dave Airlie2008-07-251-0/+4
| |/ |/| | | | | | | patch from Fedora. maybe someone can fix this later but for now lets try and release Mesa so ajax can live his life and get Xorg 7.4 out.
* | commentsBrian Paul2008-06-111-1/+10
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