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path: root/src/mesa/drivers/dri/i965
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* i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.Kenneth Graunke2011-12-185-46/+48
* i965/fs: Don't swizzle the results of textureSize().Kenneth Graunke2011-12-181-0/+3
* mesa: implement DrawTransformFeedback from ARB_transform_feedback2Marek Olšák2011-12-152-2/+4
* i965: Drop separate stencil assertions in update_draw_buffer().Eric Anholt2011-12-141-16/+0
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-076-46/+208
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-075-24/+59
* i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.Paul Berry2011-12-072-65/+111
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-073-12/+63
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
* i965: Only convert if/else to conditional adds prior to Gen6.Paul Berry2011-12-071-2/+28
* i965 gs: Remove unnecessary mapping of key->primitive.Paul Berry2011-12-072-16/+7
* i965: Set Ivybridge's is_array SURFACE_STATE bit.Kenneth Graunke2011-12-071-1/+2
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* intel: Only prefer separate stencil when we can do HiZ.Eric Anholt2011-12-071-2/+10
* i965: Set SURFACE_STATE vertical alignment bit on Ivybridge.Kenneth Graunke2011-12-061-0/+7
* i965: Fix incorrect comment about single program flow on Ironlake.Kenneth Graunke2011-12-051-1/+1
* i965: Fix emit of a MOV with bad destination channel on gen6 math in FPs.Stuart Abercrombie2011-12-021-5/+5
* mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88Brian Paul2011-12-021-1/+1
* mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88Brian Paul2011-12-021-1/+1
* i965: Make gen6_resolve_implied_move a no-op for MRF sources.Kenneth Graunke2011-12-021-0/+3
* i965/fs: Fix regression in fbo-alphatest-nocolor.Eric Anholt2011-11-301-1/+1
* i965/fs: Make register file enum 0 be the undefined register file.Eric Anholt2011-11-302-8/+25
* i965: Don't perform the precompile on fragment shaders by default.Eric Anholt2011-11-303-1/+5
* i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.Eric Anholt2011-11-292-32/+30
* i965: Fix EXT_texture_swizzle with a writemask in the FFFS/FP backend.Eric Anholt2011-11-291-6/+16
* i965: Base HW depth format setup based on MESA_FORMAT, not bpp.Eric Anholt2011-11-294-53/+39
* i965: Don't depth test the fake depthbuffer when one isn't present.Eric Anholt2011-11-291-1/+6
* mesa: Make gl_program::InputsRead 64 bits.Mathias Fröhlich2011-11-297-11/+11
* android: pass -std=c99 by defaultChia-I Wu2011-11-261-4/+0
* i965/gen6: Fix GPU hang when using stencil buffer without depthChad Versace2011-11-231-0/+5
* i965: Add support for ARGB2101010 rendering.Eric Anholt2011-11-221-1/+1
* i965: Add support for RGBA_16 unorm rendering.Eric Anholt2011-11-221-1/+1
* i965: Add support for half-float formats.Eric Anholt2011-11-221-7/+11
* i965: Reorganize MESA_FORMAT -> BRW_SURFACEFORMAT table.Eric Anholt2011-11-221-48/+146
* i965: Mark texture formats as supported using the surface formats table.Eric Anholt2011-11-221-1/+12
* i965: Use the surface format table to determine render target supportedness.Eric Anholt2011-11-224-60/+95
* intel: Add the context to the render_target_supported() vtbl method.Eric Anholt2011-11-223-4/+5
* i965: Add a table of the surface format information from the PRM.Eric Anholt2011-11-221-0/+204
* Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesaChad Versace2011-11-2219-99/+643
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| * i965/gen6: Set vertical alignment in SURFACE_STATE batchChad Versace2011-11-222-6/+11
| * intel: Store miptree alignment units in the miptreeChad Versace2011-11-221-18/+8
| * i965: Mark that depth buffer needs depth resolve after drawingChad Versace2011-11-221-0/+23
| * i965: Resolve buffers before drawing [v2]Chad Versace2011-11-221-0/+73
| * i965: Prevent recursive calls to FLUSH_VERTICES [v2]Chad Versace2011-11-221-0/+66
| * i965/gen6: Manipulate state batches for HiZ meta-ops [v4]Chad Versace2011-11-228-9/+74
| * i965/gen6: Complete stubs for HiZ buffer resolvesChad Versace2011-11-221-2/+298
| * i965: Add HiZ operation state to brw_contextChad Versace2011-11-221-0/+35
| * intel: Define struct intel_resolve_map [v2]Chad Versace2011-11-222-0/+2
| * intel: Change signature of HiZ resolve functionsChad Versace2011-11-223-15/+23
| * intel: Remove unused HiZ functionsChad Versace2011-11-221-9/+0
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