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* i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
| | | | | | | | This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
* Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-093-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
| * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
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| * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-041-0/+1
| | | | | | | | (cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
| * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-041-0/+1
| | | | | | | | | | | | We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
| * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | | | | | | | (cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
| * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | | | | | | | | | (cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
| * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | | | | | | | | | | | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
| * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | | | | | | | | | | | | | | | | | Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
| * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | | | | | | | (cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
| * i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| | | | | | | | | | | | Previously, we'd be branching based on whatever condition code happened to be laying around. (cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
| * i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
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| * i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| | | | | | | | | | Bug #20821 (cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
| * i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911. (cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
| * i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| | | | | | | | | | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
| * i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| | | | | | | | | | | | | | This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
| * i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| | | | | | | | | | | | | | | | | | | | It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
| * i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
| | | | | | | | | | The code duplication bothered me. (cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
| * i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
| | | | | | | | | | It's the last addressable byte, not the byte after the end of the buffer. (cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
| * i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
| | | | | | | | (cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
| * i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt2009-07-201-1/+2
| | | | | | | | | | | | | | Fixes everything-black with meta_clear_tris on quake4-mpdemo and doom3-demo. Bug #18844, 22077. (cherry picked from commit 81d555068408d4343d7627c8bedda5675f09bd21)
| * i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-07-044-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
| * i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-07-041-13/+11
| | | | | | | | | | | | | | Thanks to branching, the state of c->current_const[i].index at the point of emitting constant loads for this instruction may not match the actual constant currently loaded in the reg at runtime. Fixes a regression in my GLSL program for idr's class since b58b3a786aa38dcc9d72144c2cc691151e46e3d5.
| * i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| | | | | | | | | | | | | | glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling). (cherry picked from commit 4ef1f8e3b52a06fcf58f78c9c36738531b91dbac)
| * i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only GL_TEXTURE_WRAP_S should be respected). But the i965 hardware seems to follow the value of GL_TEXTURE_WRAP_T even when sampling 1D textures. This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D textures are used; this allows the texture to be sampled correctly, avoiding "imaginary" border elements in the T direction. This bug was demonstrated in the Piglit tex1d-2dborder test. With this fix, that test passes. (cherry picked from commit ab6c4fa582972e25f8800c77b5dd5b3a83afc996)
| * i965: fix segfault on low memory conditionsRobert Ellison2009-06-171-0/+7
| | | | | | | | | | | | | | | | When out of memory (in at least one case, triggered by a longrunning memory leak), this code will segfault and crash. By checking for the out-of-memory condition, the system can continue, and will report the out-of-memory error later, a much preferable outcome. (cherry picked from commit 44a4abfd4f8695809eaec07df8eeb191d6e017d7)
| * i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-06-171-2/+5
| | | | | | | | | | | | | | Noticed while debugging a weird 1D FBO testcase that left its existing viewport and projection matrix in place when switching drawbuffers. Didn't fix the testcase, though. (cherry picked from commit 3a521d84ecc646fcc65fa3fe7c5f1fdbdebe8bc2)
| * i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-06-171-8/+10
| | | | | | | | | | I don't have a testcase for this, but it seems clearly wrong. (cherry picked from commit dc657f3929fbe03275b3fae4ef84f02e74b51114)
| * i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-06-174-13/+27
| | | | | | | | | | | | | | | | | | | | | | Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying. (cherry picked from commit 0f5113deed91611ecdda6596542530b1849bb161)
* | intel: Add support for ARB_sync.Eric Anholt2009-09-032-0/+2
| | | | | | | | | | We currently weasel out of supporting the timeout parameter, but otherwise this extension looks ready, and should make the common case happy.
* | Revert "i965: Use VBOs in the VBO module on 965, now that we have ↵Eric Anholt2009-09-021-2/+0
| | | | | | | | | | | | | | | | | | | | ARB_map_buffer_range." This reverts commit 00413d87426f14df47d90ba3c995e1889e9f88ca. Even with fixes, using ARB_map_buffer_range in the VBO module isn't showing up as a significant win, and some cases apparently regressed. Bug #23624.
* | i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao2009-09-021-2/+2
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* | i965: validate sf stateXiang, Haihao2009-09-021-0/+1
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* | i965: Fix segfault with ARB_oq CheckQuery when results are already fetched.Eric Anholt2009-08-291-1/+1
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* | i965: Support PROGRAM_ENV_PARAMs in brw_vs_emit.cEric Anholt2009-08-292-1/+4
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* | i965: Use VBOs in the VBO module on 965, now that we have ARB_map_buffer_range.Eric Anholt2009-08-281-0/+2
| | | | | | | | This looks like it's a small win on blender.
* | i965: Implement ARB_oq CheckQuery in the intended way.Eric Anholt2009-08-281-6/+1
| | | | | | | | | | Previously we blocked because I hadn't added the libdrm function. Now it's there, so update your libdrm.
* | i965: Increase assmebly shader program parameter limitsIan Romanick2009-08-261-2/+2
| | | | | | | | | | Increase the number of native program parameters to the same values exposed by GLSL.
* | ARB prog: Change handling of program parameter limitsIan Romanick2009-08-261-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several changes are made to program parameter limits. Several of the non-NATIVE limits are set higher. All of the NATIVE limits are set to zero in the core Mesa code. Each driver must set the actual value in its context creation routine. If the NATIVE value remains zero, this indicates that hardware shaders may not be supported. Each of the preceeding changes matches the bahavior of Apple's shader assembler, so it seems safe. Finally, we limit the value of MaxEnvParams to be no greater than MaxNativeAttribs. At least one case has been found where an application does the wrong thing if MaxNativeAttribs < MaxEnvParams. See also bugzilla #23490.
* | i965: init the tex_units_used fieldBrian Paul2009-08-261-0/+1
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* | i965: fix incorrect tex unit in emit_tex() and emit_txb()Brian Paul2009-08-261-2/+4
| | | | | | | | | | | | | | | | The instructions we're translating already went through the brw_wm_pass_fp() function which does the sampler->texture unit mapping. We were applying the sample->unit mapping a second time in the GLSL texture emitters. Often, this made no difference but other times it could lead to accessing an invalid texture and could cause a GPU lockup.
* | i965: clean-up tex target switchesBrian Paul2009-08-261-2/+10
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* | i965: added texture unit sanity checkBrian Paul2009-08-261-0/+13
| | | | | | | | | | Check that all the textures needed by the current fragment program actually exist and are valid.
* | i965: keep track of which texture units the fragment shader accessesBrian Paul2009-08-262-3/+18
| | | | | | | | We'll use this for debug/sanity checking.
* | i965: clean up texture target switchesBrian Paul2009-08-261-2/+10
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* | i965: add some texture unit/target assertionsBrian Paul2009-08-252-0/+10
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* | i965: Implement frag prog DPH like DP4Ian Romanick2009-08-221-3/+5
| | | | | | | | | | DPH can output to any component, not just to X. This allows fpalu.c to run without hitting the assertion in emit_dph.
* | intel: Fix failure to commit -a --amend before last push.Eric Anholt2009-08-191-1/+1
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* | intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-08-191-0/+10
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* | i965: disable bounds checking on arrays with stride 0Roland Scheidegger2009-08-151-1/+1
| | | | | | | | | | | | | | | | if stride is 0 we cannot use count as max index for bounds checking, since the hardware will simply return 0 as data for indices failing bounds check. If stride is 0 any index should be valid hence simply disable bounds checking in this case. This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
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