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* [intel] Warnings fixes.Eric Anholt2008-05-022-1/+1
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* [intel] Merge intel_ioctl.h. Not sure how this slipped by in the .c merge.Eric Anholt2008-05-021-46/+0
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* [i965] short immediate values must be replicated to both halves of the dwordKeith Packard2008-04-251-2/+2
| | | | | | The 32-bit immediate value in the i965 instruction word must contain two copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to copy the value into both halves of the immediate value instruction field.
* i965: fix DEPTH_TEXTURE_MODE (bug #14220)Xiang, Haihao2008-04-222-7/+10
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* [i965] This is to fix random crash in some maps of Ut2004 demo.Zou Nan hai2008-04-221-1/+1
| | | | | | | e.g. bridge of fate. If vs output is big, driver may fall back to use 8 urb entries for vs, unfortunally, for some unknown reason, if vs is working at 4x2 mode, 8 entries is not enough, may lead to gpu hang.
* i965: fixup depth buffer checkDave Airlie2008-04-181-1/+1
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* i965: fix vb aperture space checkDave Airlie2008-04-181-4/+8
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* 965: fix vb upload size checkDave Airlie2008-04-181-3/+5
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* i965: fix gs_prog aperture checkDave Airlie2008-04-181-2/+4
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* i965: initial attempt at fixing the aperture overflowDave Airlie2008-04-1824-126/+340
| | | | | | | | | Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
* Revert "[i965] renable regative rhw test"Xiang, Haihao2008-04-173-12/+16
| | | | | This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b. rhw issue has gone away on IGD.
* i965: depth offset on glPolygonMode(GL_LINE/GL_POINT)Xiang, Haihao2008-03-281-2/+2
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* [965] Fix massively broken state cache dirty flagging.Michal Wajdeczko2008-03-261-2/+6
| | | | | It was flagging a last_bo update even when last_bo didn't change, but another part was failing to update last_bo when it should have.
* [965] Don't let the negate flags of src0 affect 1 constants in precalc_dst/litEric Anholt2008-03-261-14/+21
| | | | | This patch is a variant of a submission by Michal Wajdeczko to fix oglconform fpalu failures.
* [965] Correctly set read mask for OPCODE_SWZ in pass1.Michal Wajdeczko2008-03-261-1/+1
| | | | | | While OPCODE_SWZ has usually been optimized away in pass0, it may still exist if a SWZ with dst saturate was emitted in pass_fp. Fixes an error in oglconform fpalu.c.
* [965] Clean up whitespace and dead code from do_unfilled change.Eric Anholt2008-03-261-11/+6
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* [965] Avoid emitting dead code for DPx/math instructions.Michal Wajdeczko2008-03-211-0/+15
| | | | | | The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted.
* [965] Improve pinterp performance by delaying reads of just-written regs.Michal Wajdeczko2008-03-211-0/+4
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* [965] Fix negating of unsigned value in emit_wpos_xy.Michal Wajdeczko2008-03-211-1/+1
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* [965] Add MVP code for position invariant vertex programs.Michal Wajdeczko2008-03-211-0/+3
| | | | This fixes the arbvptorus demo.
* [965] Shuffle state flags to match the order we initialize them in.Michal Wajdeczko2008-03-211-2/+2
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* [i965] multiple rendering target fixZou Nan hai2008-03-212-10/+29
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* [965] Initialize region surface key structure padding.Eric Anholt2008-03-191-0/+2
| | | | Fixes valgrind warnings, and potential performance loss from cache misses.
* Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and ↵Zou Nan hai2008-03-182-3/+3
| | | | | | | GL_LINE_STRIP" There is no information in GS to determinate when to reset line stipple count, still fallback to software This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
* [i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIPZou Nan hai2008-03-182-3/+3
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* [965] Fix fp temp reg release code to not usually release all temps.Andrzej Trznadel2008-03-171-2/+2
| | | | Also, use wrapped ffs() instead of native.
* [i965] round pointsize to nearest int according to specZou Nan hai2008-03-171-2/+2
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* [i965] fix wpos height 1 pixel higherZou Nan hai2008-03-172-2/+2
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* intel: fix abort issue with shadowtex demo when useXiang, Haihao2008-03-141-0/+3
| | | | DEPTH_STENCIL texture. (bug#14952).
* [i965] multiple rendering target supportZou Nan hai2008-03-1311-80/+102
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* [i965] fix fd.o bug #11471 and #11478Zou Nan hai2008-03-073-8/+23
| | | | | 1. Follow EXT_texture_rectangle with YCbCr texture 2. swap UV component for MESA_FORMAT_YCBCR
* i965: Fix double free issue to pass glean/maskedClear testXiang, Haihao2008-03-061-0/+1
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* i965:fix segfault issue when clearing the window whichXiang, Haihao2008-03-061-1/+2
| | | | | is created with mode GLUT_SINGLE|GLUT_RGB|GLUT_DEPTH. This issue is introduced by 20b8bff49cba3e8246e29004c5ff38f231d589ff
* i965: use _Current pointer instead of Current pointer.Xiang, Haihao2008-02-293-23/+5
| | | | fix double free issue(bug#14710). It also corrects glsl/bitmap demo behavior.
* [965] Fix conditional sequencing to allow the frame_buffer_texobj case.Eric Anholt2008-02-281-8/+6
| | | | | Previously the frame_buffer_texobj case would have been bound as a normal texture, at best resulting in no surface data being associated with it.
* [965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt2008-02-284-22/+54
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* [965] Fix serious copy'n'paste failure in brw state dumping.Eric Anholt2008-02-281-3/+3
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* intel: Always use intelInitExtensions() for initializing extensions.Kristian Høgsberg2008-02-271-15/+0
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* i965: Setup framebuffer texture in meta_draw_region.Kristian Høgsberg2008-02-264-7/+12
| | | | | | | With DRI2 we there is no screen region until a drawable is bound to the context. Set up the framebuffer texture in meta_draw_region instead which should also handle the case where the draw region changes as a result of resizing a redirected window or resizing the screen.
* [965] Don't segfault on INTEL_DEBUG=batch when a surface buffer is NULL.Eric Anholt2008-02-261-0/+4
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* [965] remove dead brw_parameter_list_state_flags.Eric Anholt2008-02-261-80/+0
| | | | This was replaced by Mesa core code.
* intel: Add missing include file to silence last couple of warnings.Kristian Høgsberg2008-02-251-0/+1
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* i965: fix assertion failure caused by commit ↵Xiang, Haihao2008-02-251-0/+3
| | | | dd1d66fc4ab5d7064113a2017a431c3461598b91.
* intel: Merge intel_context.c from i915 and i965.Kristian Høgsberg2008-02-222-831/+14
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* Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg2008-02-225-454/+7
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* Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.hAlan Hourihane2008-02-222-11/+10
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* fix compile for previous commitZou Nan hai2008-02-191-1/+1
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* [i965] fix broken glsl texdemo1Zou Nan hai2008-02-191-1/+8
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* i965: don't swizzle fogcoord if FogOption is FOG_NONE.Xiang, Haihao2008-02-151-0/+5
| | | | fix #10788 issue on 965.
* i965: use setup attributes as inputs when allocating registersXiang, Haihao2008-02-143-3/+4
| | | | for WM payload. fix #10767
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