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authorZou Nan hai <[email protected]>2008-02-19 14:47:57 +0800
committerZou Nan hai <[email protected]>2008-02-19 14:47:57 +0800
commit689ff273d18528ec12817124cfbc6a8159cd8497 (patch)
tree8c8cc3e4b84b4b99dcc06c92e07ed30f4d2adcba /src/mesa/drivers/dri/i965
parentba38909be21e4b33121b87bb7ac8743886a4f706 (diff)
[i965] fix broken glsl texdemo1
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_pass2.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 8541cbcbec0..766edc8dacc 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -86,8 +86,15 @@ static void init_registers( struct brw_wm_compile *c )
for (j = 0; j < FRAG_ATTRIB_MAX; j++)
if (inputs & (1<<j)) {
+ /* index for vs output and ps input are not the same
+ in shader varying */
+ GLuint index;
+ if (j > FRAG_ATTRIB_VAR0)
+ index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0)
+ else
+ index = j;
nr_interp_regs++;
- prealloc_reg(c, &c->payload.input_interp[j], i++);
+ prealloc_reg(c, &c->payload.input_interp[index], i++);
}
assert(nr_interp_regs >= 1);