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path: root/src/mesa/drivers/dri/i965/gen8_depth_state.c
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* i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.Kenneth Graunke2014-06-161-4/+16
* i965/gen8: Set depth extent fieldJordan Justen2014-05-131-1/+1
* i965/gen8 depth: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-2/+2
* i965/Gen8: Set up layer constraints properly for depth buffersChris Forbes2014-05-091-9/+6
* i965: Delete the intel_regions.c code.Eric Anholt2014-05-011-1/+0
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-7/+7
* i965: Make Broadwell HiZ path arrange for TC flushes.Kenneth Graunke2014-04-221-0/+3
* i965/gen7: Skip repeated NULL depth/stencil state emits.Eric Anholt2014-04-111-0/+8
* i965: Set Broadwell MOCS values everywhere it's possible.Kenneth Graunke2014-03-251-3/+4
* i965: Implement HiZ resolves on Broadwell.Kenneth Graunke2014-02-191-0/+103
* i965: Refactor Gen8 depth packet emission.Kenneth Graunke2014-02-191-72/+99
* i965: Program 3DSTATE_HIER_DEPTH_BUFFER properly on Broadwell.Kenneth Graunke2014-02-191-8/+17
* i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.Kenneth Graunke2014-01-311-0/+169