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path: root/src/mesa/drivers/dri/i965/gen7_l3_state.c
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* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-301-1/+1
* i965: drop brw->is_baytrail in favor of devinfo->is_baytrailLionel Landwerlin2017-08-301-3/+3
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-301-1/+2
* i965: Stop looking at NewDriverState when emitting 3DSTATE_URBJason Ekstrand2017-08-181-0/+9
* mesa: use gl_program for CurrentProgram rather than gl_shader_programTimothy Arceri2017-01-231-3/+3
* i965: add a kernel_features bitfield to intel screenIago Toral Quiroga2017-01-051-1/+1
* i965: get rid of brw->can_do_pipelined_register_writesIago Toral Quiroga2017-01-051-2/+3
* st/mesa/glsl/nir/i965: make use of new gl_shader_program_data in gl_shader_pr...Timothy Arceri2016-11-191-2/+2
* i965: use L3 data cache for SSBOsLionel Landwerlin2016-10-051-1/+2
* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-4/+4
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-5/+5
* intel: Pull the guts of gen7_l3_state.c into a shared helperJason Ekstrand2016-09-031-331/+37
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-8/+8
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-231-0/+1
* i965: Consider tessellation in get_pipeline_state_l3_weights.Kenneth Graunke2016-02-111-1/+6
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-081-2/+2
* i965: Invalidate state cache before L3 partitioning set-up.Francisco Jerez2016-02-081-0/+1
* i965: Fix cache pollution race during L3 partitioning set-up.Francisco Jerez2016-02-081-8/+23
* i965: Work around L3 state leaks during context switches.Francisco Jerez2015-12-091-4/+57
* i965: Add debug flag to print out the new L3 state during transitions.Francisco Jerez2015-12-091-0/+17
* i965: Implement L3 state atom.Francisco Jerez2015-12-091-0/+81
* i965: Calculate appropriate L3 partition weights for the current pipeline state.Francisco Jerez2015-12-091-0/+53
* i965: Implement selection of the closest L3 configuration based on a vector o...Francisco Jerez2015-12-091-0/+95
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez2015-12-091-1/+1
* i965/hsw: Enable L3 atomics.Francisco Jerez2015-12-091-0/+14
* i965: Implement programming of the L3 configuration.Francisco Jerez2015-12-091-0/+95
* i965: Import tables enumerating the set of validated L3 configurations.Francisco Jerez2015-12-091-0/+167
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