aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/gen6_depth_state.c
Commit message (Expand)AuthorAgeFilesLines
* i965: Use ISL for emitting depth/stencil/hiz state on gen6+Jason Ekstrand2018-05-081-221/+0
* i965: Re-order depth/stencil/hiz/clear packets to match ISLJason Ekstrand2018-05-081-17/+17
* i965: Add and use a single miptree aux_buf fieldNanley Chery2018-04-241-3/+3
* i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson2017-08-041-9/+3
* i965/miptree: Clean-up unusedTopi Pohjolainen2017-07-221-6/+2
* i965: Drop redundant check for non-tiled depth bufferTopi Pohjolainen2017-07-201-2/+1
* i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen2017-07-201-1/+1
* i965/miptree: Switch to isl_surf::tilingTopi Pohjolainen2017-07-201-1/+1
* i965/miptree/gen7+: Use isl for hiz layoutsTopi Pohjolainen2017-06-191-3/+3
* i965/gen6: Use isl for hizTopi Pohjolainen2017-06-191-8/+4
* i965/gen6: Use isl for stencil surfacesTopi Pohjolainen2017-06-191-19/+12
* i965/gen6: Remove dead code in hiz surface setupTopi Pohjolainen2017-06-171-7/+6
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-071-1/+6
* i965: Rework Sandy Bridge HiZ and stencil layoutsJason Ekstrand2017-06-011-2/+2
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-2/+2
* i965/gen6: Remove check for stencil formatTopi Pohjolainen2017-01-271-14/+8
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offsetJason Ekstrand2016-10-271-4/+2
* i965: Assert that a depth_mt exists when using HiZ.Matt Turner2016-05-251-0/+1
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-1/+1
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-7/+0
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-151-2/+32
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-151-8/+27
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-151-0/+2
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-151-0/+3
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-151-0/+3
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-151-0/+33
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-151-0/+176
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 00:46:19 +0000