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path: root/src/mesa/drivers/dri/i965/brw_wm_pass2.c
Commit message (Expand)AuthorAgeFilesLines
* i965: Remove the old ARB_fragment_program backend.Eric Anholt2012-10-081-359/+0
* i965: Don't use brw->fragment_program in the old brw_wm_pass2.c.Kenneth Graunke2012-09-051-1/+1
* i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS.Olivier Galibert2012-08-091-1/+13
* mesa: put _mesa_ prefix on vert_result_to_frag_attrib()Brian Paul2011-09-061-1/+1
* Refactor code that converts between gl_vert_result and gl_frag_attrib.Paul Berry2011-09-061-8/+1
* i965: Fix gen6 interpolation setup for 16-wide.Eric Anholt2010-12-061-15/+26
* i965: Move payload reg setup to compile, not lookup time.Eric Anholt2010-12-061-2/+2
* intel: Annotate debug printout checks with unlikely().Eric Anholt2010-11-031-2/+2
* i965: Align the number of payload regs to 2 again in 16-wide mode.Eric Anholt2010-08-301-1/+1
* i965: Rename nr_depth_regs to nr_payload_regs.Eric Anholt2010-08-201-2/+2
* Merge branch 'outputswritten64'Ian Romanick2009-11-171-2/+2
* i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-05-141-8/+10
* i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-05-141-2/+1
* i965: whitespace changes and reformattingBrian Paul2009-01-221-15/+13
* fix compile for previous commitZou Nan hai2008-02-191-1/+1
* [i965] fix broken glsl texdemo1Zou Nan hai2008-02-191-1/+8
* i965: use setup attributes as inputs when allocating registersXiang, Haihao2008-02-141-1/+2
* support branch and loop in pixel shaderZou Nan hai2007-06-211-1/+1
* Update DRI drivers for new glsl compiler.Brian2007-02-231-3/+1
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+338
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