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path: root/src/mesa/drivers/dri/i965/brw_wm_glsl.c
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* i965: Nuke brw_wm_glsl.c.Eric Anholt2010-12-061-1035/+0
* i965: Move payload reg setup to compile, not lookup time.Eric Anholt2010-12-061-4/+4
* intel: Annotate debug printout checks with unlikely().Eric Anholt2010-11-031-4/+4
* i965: Add support for pull constants to the new FS backend.Eric Anholt2010-10-221-22/+20
* i965: fix const register count for sandybridgeZhenyu Wang2010-09-281-2/+2
* i965: enable accumulator update in PS kernel too on sandybridgeZhenyu Wang2010-09-281-0/+3
* i965: Set up inputs to the fragment shader according to FP InputsRead.Eric Anholt2010-09-281-17/+33
* i965: Add support for attribute interpolation on Sandybridge.Eric Anholt2010-09-281-0/+2
* i965: Share the KIL_NV implementation between glsl and non-glsl.Eric Anholt2010-09-211-16/+1
* intel: Remove noise opcode support from i915 and i965 driversIan Romanick2010-09-101-1120/+0
* i965: Make brw_CONT and brw_BREAK take the pop count.Eric Anholt2010-08-301-5/+2
* i965: Set the pop count on BRK/CONT inside of an if statement in the FS.Eric Anholt2010-08-271-4/+11
* i965: Rename nr_depth_regs to nr_payload_regs.Eric Anholt2010-08-201-3/+3
* i965: More s/stderr/stdout/ for program debug.Eric Anholt2010-08-091-1/+1
* Merge remote branch 'origin/master' into glsl2Eric Anholt2010-07-261-3/+3
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| * mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul2010-06-101-3/+3
* | i965: Add support for the DP2 opcode, which we use for dot(vec2, vec2).Eric Anholt2010-07-021-0/+3
* | i965: Add support for OPCODE_SSG.Eric Anholt2010-06-301-0/+3
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* i965: Dump out the correct shared function for SEND on Ironlake.Eric Anholt2010-05-141-1/+1
* intel: Clean up chipset name and gen num for IronlakeZhenyu Wang2010-04-211-1/+1
* i965: Handle the negate and abs swizzles on brw_wm_glsl.c immediate args.Eric Anholt2010-03-241-2/+12
* i965: Allow FS constants to be used as immediates instead of push/pull.Eric Anholt2010-03-221-6/+19
* i965: Add INTEL_DEBUG=glsl_force to force brw_wm_glsl.c.Eric Anholt2010-03-221-0/+3
* i965: Use the PLN instruction when possible in interpolation.Eric Anholt2010-03-101-0/+38
* i965: Add support for the CMP opcode in the GLSL path.Eric Anholt2010-03-101-0/+3
* i965: Print the opcode name for unrecognized opcodes in the GLSL path.Eric Anholt2010-03-101-2/+3
* i965: Fix ENDLOOP to only patch up this loop's BREAK and CONT.Eric Anholt2010-03-091-2/+4
* i965: Unalias all GLSL source regs from the destination regs used.Eric Anholt2010-03-091-113/+25
* Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg2010-02-191-5/+5
* Merge branch 'mesa_7_7_branch'Brian Paul2009-12-311-1/+1
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| * intel: Silence compiler warnings.Vinson Lee2009-12-281-1/+1
* | i965: Extra asserts on flow control instructions to clarify for clang.Eric Anholt2009-12-261-1/+3
* | i965: Clean up double initialization of dst_flags from a rebase resolve.Eric Anholt2009-12-261-4/+0
* | intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt2009-12-221-1/+2
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* Merge branch 'outputswritten64'Ian Romanick2009-11-171-1/+1
* i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-131-71/+5
* i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt2009-11-131-89/+6
* i965: Clean up Ironlake sampler type definitions.Eric Anholt2009-11-131-3/+3
* i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-061-50/+52
* i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-061-98/+3
* i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-249/+8
* i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-061-168/+9
* i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-061-66/+12
* i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-24/+1
* i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-84/+3
* i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-061-39/+59
* i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-061-19/+1
* i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-061-101/+5
* i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-061-7/+15
* i965: use macros to get/set prog_instruction::Aux fieldBrian Paul2009-10-291-2/+2
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