aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_vec4.cpp
Commit message (Expand)AuthorAgeFilesLines
* i965/fs: calculate first non-payload GRF using attrib slotsJuan A. Suarez Romero2016-05-171-0/+1
* i965/vec4: use attribute slots to calculate URB read lengthJuan A. Suarez Romero2016-05-171-3/+9
* i965/fs: Stop setting dispatch_grf_start_reg from the visitorJason Ekstrand2016-05-141-0/+2
* i965: Pass devinfo pointer to is_3src() helpers.Francisco Jerez2016-05-031-1/+1
* i965: Pass devinfo pointer to brw_instruction_name().Francisco Jerez2016-05-031-1/+1
* i965: Properly handle integer types in opt_vector_float().Kenneth Graunke2016-04-201-4/+18
* i965: Make opt_vector_float() only handle non-type-conversion MOVs.Kenneth Graunke2016-04-201-2/+5
* i965: Fold vectorize_mov() back into the one caller.Kenneth Graunke2016-04-201-24/+16
* i965: Rework opt_vector_float() control flow.Kenneth Graunke2016-04-201-27/+34
* i965/vec4: Handle MOV_INDIRECT in pack_uniform_registersJason Ekstrand2016-04-151-0/+18
* i965/vec4: Add support for SHADER_OPCODE_MOV_INDIRECTJason Ekstrand2016-04-151-0/+1
* i965/vec4: Use can_do_writemask in can_reswizzleJason Ekstrand2016-04-151-3/+5
* i965/vec4: Move can_do_writemask to vec4_instructionJason Ekstrand2016-04-151-0/+28
* i965/vec4: Get rid of the uniform_size arrayJason Ekstrand2016-04-141-8/+0
* i965/vec4: Use MOV_INDIRECT instead of reladdr for indirect push constantsJason Ekstrand2016-04-141-1/+1
* i965: Remove the RCP+RSQ algebraic optimizationsJason Ekstrand2016-03-221-11/+0
* i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.Francisco Jerez2016-03-141-0/+1
* i965/vec4: add opportunistic behaviour to opt_vector_float()Juan A. Suarez Romero2016-03-041-21/+39
* i965: Eliminate brw_nir_lower_{inputs,outputs,io} functions.Kenneth Graunke2016-02-261-3/+3
* i965: Lower min/max after optimization on Gen4/5.Matt Turner2016-02-171-0/+38
* i965: Fix gl_DrawID in the vec4 backend.Kenneth Graunke2016-02-141-5/+5
* i965: Rename optimizer debug 00 filenameBen Widawsky2016-02-121-1/+1
* i965/vec4: Drop support for ATTR as an instruction destination.Kenneth Graunke2016-02-091-16/+0
* i965: Apply VS attribute workarounds in NIR.Kenneth Graunke2016-02-091-0/+3
* i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.Kenneth Graunke2016-02-091-1/+1
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-151-1/+1
* i965: Make an is_scalar boolean in brw_compile_vs().Kenneth Graunke2016-01-141-5/+5
* i965: Move 3-src subnr swizzle handling into the vec4 backend.Kenneth Graunke2016-01-021-0/+13
* i965: Add support for gl_DrawIDARB and enable extensionKristian Høgsberg Kristensen2015-12-291-1/+12
* i965: Add support for gl_BaseVertexARB and gl_BaseInstanceARBKristian Høgsberg Kristensen2015-12-291-2/+5
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-281-0/+1
* i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.Kenneth Graunke2015-12-281-0/+1
* i965: Port tessellation evaluation shaders to vec4 mode.Kenneth Graunke2015-12-281-0/+1
* i965: Add tessellation control shaders.Kenneth Graunke2015-12-221-1/+9
* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-301-0/+29
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-7/+0
* i965: Prevent implicit upcasts to brw_reg.Matt Turner2015-11-241-2/+3
* i965: Use scope operator to ensure brw_reg is interpreted as a type.Matt Turner2015-11-241-2/+2
* i965: Use implicit backend_reg copy-constructor.Matt Turner2015-11-241-4/+2
* i965: Add and use backend_reg::equals().Matt Turner2015-11-241-4/+2
* i965: Use nir_lower_tex for texture coordinate loweringJason Ekstrand2015-11-231-0/+2
* i965: Move postprocess_nir to codegen timeJason Ekstrand2015-11-231-1/+5
* i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.Matt Turner2015-11-191-5/+1
* i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().Matt Turner2015-11-191-55/+12
* i965: Convert scalar_* flags to a scalar_stage array.Kenneth Graunke2015-11-161-2/+2
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-131-1/+1
* i965: Combine register file field.Matt Turner2015-11-131-10/+6
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-131-83/+58
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-16/+16
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-52/+48
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 13:25:00 +0000