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drivers
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dri
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i965
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brw_urb.c
Commit message (
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Author
Age
Files
Lines
*
intel: Clean up chipset name and gen num for Ironlake
Zhenyu Wang
2010-04-21
1
-1
/
+1
*
Replace the _mesa_*printf() wrappers with the plain libc versions
Kristian Høgsberg
2010-02-19
1
-3
/
+3
*
intel: Replace IS_G4X() across the driver with context structure usage.
Eric Anholt
2009-12-22
1
-4
/
+5
*
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Eric Anholt
2009-12-22
1
-1
/
+2
*
i965: add support for new chipsets
Xiang, Haihao
2009-07-13
1
-1
/
+11
*
i965: Increase G4X default VS URB allocation to actually allow 32 threads.
Eric Anholt
2009-06-30
1
-3
/
+14
*
i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.
Eric Anholt
2008-11-12
1
-1
/
+1
*
i965: Add a big comment explaining my understanding of URB management.
Eric Anholt
2008-11-12
1
-1
/
+38
*
i965: Fix copy'n'paste issue that made brw->urb.constrained useless.
Eric Anholt
2008-11-02
1
-3
/
+7
*
Revert "Revert "Merge branch 'drm-gem'""
Dave Airlie
2008-08-24
1
-14
/
+1
*
Revert "Merge branch 'drm-gem'"
Dave Airlie
2008-08-24
1
-1
/
+14
*
intel-gem: Update to new check_aperture API for classic mode.
Eric Anholt
2008-08-08
1
-2
/
+1
*
965: cleanups to state emission from aperture checking and state ordering.
Eric Anholt
2008-08-08
1
-12
/
+0
*
[i965] This is to fix random crash in some maps of Ut2004 demo.
Zou Nan hai
2008-04-22
1
-1
/
+1
*
i965: initial attempt at fixing the aperture overflow
Dave Airlie
2008-04-18
1
-2
/
+3
*
i965: remove unused hal hooks
Dave Airlie
2008-02-14
1
-15
/
+0
*
i965: new integrated graphics chipset support
Xiang, Haihao
2008-01-29
1
-4
/
+4
*
i965: The given urb layout(maximal size of urb entries and the
Xiang, Haihao
2007-03-25
1
-1
/
+1
*
VS nr of urb entries is constrained to be one of a fixed set of values,
Keith Whitwell
2006-09-14
1
-2
/
+2
*
Potential fix for doom3 lockups. Seems that there is a conflict
Keith Whitwell
2006-09-12
1
-1
/
+1
*
Add Intel i965G/Q DRI driver.
Eric Anholt
2006-08-09
1
-0
/
+215