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* i965: Make gen7_pi field of brw_instruction use unsigned instead of GLuintKristian Høgsberg2014-06-091-12/+12
| | | | | | | | Nothing else uses GL-types here. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: add struct and SFID for pixel interpolator messagesChris Forbes2014-01-181-0/+21
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* i965: Don't use GL types in files shared with intel-gpu-tools.Kenneth Graunke2013-12-051-809/+809
| | | | | | | | | sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Drop trailing whitespace from files shared with intel-gpu-tools.Kenneth Graunke2013-12-051-234/+234
| | | | | | Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for DP message descriptor fields.Kenneth Graunke2013-07-151-3/+3
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove some dead code.Kenneth Graunke2013-07-031-31/+0
| | | | | | | A random smattering of things that just aren't used anymore. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Add Gen7+ fields to brw_instruction and add comments.Matt Turner2013-05-061-12/+19
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965: Replace structs with bit-shifting for Gen7 SURFACE_STATE entries.Kenneth Graunke2013-01-031-102/+0
| | | | | | | | | | | | | | | | | Every generation except Gen7 creates SURFACE_STATE entries via a uint32_t array. Only Gen7 uses the older bitfield structure, which we moved away from because it was less efficient. Convert it for consistency. This reduces the compiled size of gen7_wm_surface_state.o by 2.86% in a release build. v2: Fix accidental use of BRW_SURFACE_WIDTH/HEIGHT in brw_state_dump.c; switch back to gen7_set_surface_mcs_info setting surf[6] directly (both per Eric's review comments). Acked-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move BRW_MAX_GRF and similar defines to brw_reg.h.Kenneth Graunke2012-12-151-18/+0
| | | | | | These don't really belong in brw_structs.h. Reviewed-by: Eric Anholt <[email protected]>
* i965: Add the new flag_reg_nr instruction field from IVB.Eric Anholt2012-12-111-4/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Correct the name and usage of the flag subregister number field.Eric Anholt2012-12-111-5/+5
| | | | | | | We've been calling it a register number, it's actually the subregister, and things will get confusing once we start using it if it isn't fixed. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove bogus flag_reg_nr field from bits3.Eric Anholt2012-12-111-4/+2
| | | | | | | There's a flag subreg nr field in bits2 next to src0.vertstride, but there shouldn't be anything in bits3 next to src1.vertstride. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for instruction compaction.Eric Anholt2012-09-171-0/+26
| | | | | | | | | | | | | | | This reduces program size by using some smaller encodings for common bit patterns in the Gen ISA, with the hope of making programs fit in the instruction cache better. v2: Use larger bitshifts for the uncompressed field setups, in line with the way it's described in the spec. Consistently name a brw_compile "p" like all other code. Add a couple more tests. Consistently call things "compacted" not "compressed" (which is a different feature). Drop the explicit check for not compacting SENDs, which is unjustified and already implied by our lack of support for immediate values. Reviewed-by: Paul Berry <[email protected]>
* i965: Fix typo in shader channel select field name.Kenneth Graunke2012-07-271-4/+4
| | | | | | "chanel" isn't very searchable. I can type, honest! Signed-off-by: Kenneth Graunke <[email protected]>
* i965/msaa: Add CMS MSAA settings to brw_structs.h.Paul Berry2012-07-111-2/+20
| | | | | | | Previously the DWORD used to control the CMS MSAA layout was just a pad value, because we didn't use it. Reviewed-by: Chad Versace <[email protected]>
* i965: Set "Shader Channel Select" fields in Haswell's SURFACE_STATE.Kenneth Graunke2012-03-301-1/+8
| | | | | | | | | | | | These can be used to implement EXT_texture_swizzle without baking state-dependent swizzle instructions into the shader and forcing recompiles. For now, just set them to pass-through mode, so everything continues to work as it did on Ivybridge. We can optimize this later. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for the MAD opcode on gen6+.Eric Anholt2012-02-101-0/+37
| | | | | | v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/fs: Fix rendering corruption in unigine tropics.Eric Anholt2012-01-301-0/+11
| | | | | | | | | | | | We were allocating registers into the MRF hack region, resulting in sparkly renering in a few of the scenes. We could do better allocation by making an MRF class, having MRFs conflict with the corresponding GRFs, and tracking the live intervals of the "MRF"s and setting up the conflicts. But this is way easier for the moment. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace a should-never-happen fallback with asserts where it matters.Eric Anholt2011-11-111-2/+0
| | | | | | | | | | | | We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and 1 more element will get used for gl_VertexID/gl_InstanceID. So it should never have been possible to hit this fallback, unless there was another bug. If you do hit this, you're probably using gl_VertexID and falling back to swrast won't work for you anyway. This also updates the limits for gen6+. Reviewed-by: Ian Romanick <[email protected]>
* i965: Document most of the brw_instruction message structs.Kenneth Graunke2011-10-181-39/+79
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename pixel_scoreboard_clear to last_render_target for clarity.Kenneth Graunke2011-10-181-4/+4
| | | | | | | | | | | | | | | | | Finding this bit in the documentation proved challenging. It wasn't in the SEND instruction's message descriptor section, nor the data port message descriptor section. It turns out to be part of the Render Target Write message's control bits, and in the documentation is named "Last Render Target Select". Shaders that use Multiple Render Targets should set this bit on the last RT write, but not on any prior ones. The GPU does update the Pixel Scoreboard appropriately, but doesn't document this bit as directly causing a scoreboard clear. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Document the brw_instruction Message Descriptor structures.Kenneth Graunke2011-10-181-2/+27
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove unused structures for command packets.Kenneth Graunke2011-07-071-433/+0
| | | | | | | | | We simply emit these using OUT_BATCH and bitshifting, as it results in better compiled code than packed structures. Since our documentation is public, it's not terribly useful to keep these around for reference. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.Kenneth Graunke2011-07-071-8/+0
| | | | | | | | This is a little different from most because it's a single DWord; there's no length field. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.Kenneth Graunke2011-07-071-9/+0
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove brw_surface_state struct that is now unused.Eric Anholt2011-05-311-74/+0
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge.Kenneth Graunke2011-05-171-0/+1
| | | | | | | | | | Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix sampler message descriptor on Ivybridge.Kenneth Graunke2011-05-171-0/+12
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix SAMPLER_STATE on Ivybridge.Kenneth Graunke2011-05-171-0/+48
| | | | | | | Most of this code copied from brw_wm_sampler_state.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update SURFACE_STATE for Ivybridge.Kenneth Graunke2011-05-171-0/+78
| | | | | | | | I'm still not happy with the amount of code duplication here, but it will have to do for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix the URB write message descriptor on Ivybridge.Kenneth Graunke2011-05-171-0/+14
| | | | | | | The message header is still incorrect, but this is a start. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix render target writes on Ivybridge.Kenneth Graunke2011-05-171-0/+16
| | | | | | | Ivybridge shifts the data port messages by one bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Viewport state setup.Kenneth Graunke2011-05-171-0/+22
| | | | | | | | | | | SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT; SF_CLIP and CC state pointers can now be uploaded independently. Some portions of the hardware documentation refer to separate upload commands for SF and CLIP; these are outdated and incorrect. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename dp_render_target struct to gen6_dp.Kenneth Graunke2011-05-131-1/+1
| | | | | | | | | This is actually just the message descriptor for Gen6+ dataport access; it has nothing to do with the render cache. Access to the sampler cache and constant cache also would use this struct; rename for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove dead vertex buffer structs.Kenneth Graunke2011-04-201-25/+0
| | | | We do this OUT_BATCH-style in brw_draw_upload.c.
* i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.Kenneth Graunke2011-04-181-19/+0
| | | | | | | | | | Most of the newer portions of the code use OUT_BATCH style. I prefer this style because it offers a clear distinction between a) hardware messages/structures with a mandatory format, and b) data structures for our own internal use that we can format however we want. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add new HiZ related bits to WM_STATE.Kenneth Graunke2011-01-101-1/+8
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* i965: Correct the dp_read message descriptor setup on g4x.Eric Anholt2010-12-231-0/+12
| | | | | | | It's mostly like gen4 message descriptor setup, except that the sizes of type/control changed to be like gen5. Fixes 21 piglit cases on gm45, including the regressions in bug #32311 from increased VS constant buffer usage.
* i965: remove unused variable since brw_wm_glsl.c removal.Eric Anholt2010-12-091-1/+1
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* i965: Set render_cache_read_write surface state bit on gen6 constant surfs.Eric Anholt2010-12-091-0/+5
| | | | This is said to be required in the spec, even when you aren't doing writes.
* i965: Set up the correct texture border color state struct for Ironlake.Eric Anholt2010-12-091-0/+9
| | | | | This doesn't actually fix border color on Ironlake, but it appears to be a requirement, and gen6 needs it too.
* i965: Add support for gen6 BREAK ISA emit.Eric Anholt2010-12-011-0/+15
| | | | | There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
* i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt2010-10-061-0/+12
| | | | | | The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
* i965: fix scissor state on sandybridgeZhenyu Wang2010-09-281-3/+5
| | | | | Fix incorrect scissor rect struct and missed scissor state pointer setting for sandybridge.
* i965: Fix sampler on sandybridgeZhenyu Wang2010-09-281-6/+8
| | | | Sandybridge has not much change on texture sampler with Ironlake.
* i965: fix depth test on sandybridgeZhenyu Wang2010-08-311-1/+1
| | | | | | | | | This includes several corrections for fixing depth test on sandybridge. Fix wrong bits definition in depth stencil state. Fix wrong order of state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use buffer width parameter in depth buffer setting. Signed-off-by: Zhenyu Wang <[email protected]>
* i965: Set the destination horiz stride even for da16, as SNB seems to need it.Zhenyu Wang2010-08-201-2/+2
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* i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang2010-08-201-2/+3
| | | | Whenever the accumulator results are needed, this bit must be set.
* i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt2010-07-081-2/+3
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