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path: root/src/mesa/drivers/dri/i965/brw_pipe_control.c
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* i965/drm: Use our internal libdrm (drm_bacon) rather than the real one.Kenneth Graunke2017-04-101-3/+3
* i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().Francisco Jerez2016-12-141-0/+1
* i965: Remove useless (harmful) assertionBen Widawsky2016-09-281-1/+1
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-1/+1
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-1/+1
* i965: Fix remaining flush vs invalidate race conditions in brw_emit_pipe_cont...Francisco Jerez2016-07-071-0/+18
* i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+10
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-10/+11
* i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.Kenneth Graunke2016-03-281-2/+0
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-081-1/+1
* i965: Only apply CS stall workaround pre-SKLBen Widawsky2015-12-211-2/+4
* i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.Francisco Jerez2015-12-091-1/+3
* i965/gen8+: Skip depth stalls on state changeBen Widawsky2015-09-081-0/+8
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-6/+34
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-4/+4
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-241-0/+331
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