| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush. | Francisco Jerez | 2016-07-07 | 1 | -10/+11 |
| * | i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs. | Kenneth Graunke | 2016-03-28 | 1 | -2/+0 |
| * | i965: Rename define for the PIPE_CONTROL DC flush bit. | Francisco Jerez | 2016-02-08 | 1 | -1/+1 |
| * | i965: Only apply CS stall workaround pre-SKL | Ben Widawsky | 2015-12-21 | 1 | -2/+4 |
| * | i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set. | Francisco Jerez | 2015-12-09 | 1 | -1/+3 |
| * | i965/gen8+: Skip depth stalls on state change | Ben Widawsky | 2015-09-08 | 1 | -0/+8 |
| * | i965: Move pipecontrol workaround bo to brw_pipe_control | Chris Wilson | 2015-07-08 | 1 | -6/+34 |
| * | i965: Rename intel_emit* to reflect their new location in brw_pipe_control | Chris Wilson | 2015-06-24 | 1 | -4/+4 |
| * | i965: Transplant PIPE_CONTROL routines to brw_pipe_control | Chris Wilson | 2015-06-24 | 1 | -0/+331 |
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