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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
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* i965: Move intel_context::vtbl to brw_context.Kenneth Graunke2013-07-091-4/+4
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-17/+12
* i965: NULL check depth_mt to quiet static analysis.Matt Turner2013-06-291-1/+1
* i965: Emit invariant state once at startup on Gen6+.Kenneth Graunke2013-06-101-2/+3
* i965: Kill software primitive counting entirely.Kenneth Graunke2013-05-211-13/+0
* i965/gen7: fix 3DSTATE_LINE_STIPPLE_PATTERNChia-I Wu2013-04-241-3/+14
* i965: Fix an unused variable warning in the release build.Eric Anholt2013-04-121-4/+2
* i965: Remove brw_context::depthstencil::hiz_mtChad Versace2013-04-101-2/+0
* intel: Replace checks for hiz_mt with intel_has*hiz()Chad Versace2013-04-101-16/+16
* i965: Change signature of brw_get_depthstencil_tile_masks()Chad Versace2013-04-101-1/+6
* i965: Reduce code duplication in handling of depth, stencil, and HiZ.Paul Berry2013-04-021-89/+106
* i965: Avoid unnecessary copy when depthstencil workaround invoked by clear.Paul Berry2013-03-191-5/+26
* intel: Make intel_region's pitch be bytes instead of pixels.Eric Anholt2013-01-181-3/+3
* i965: Add perf debug for depth/stencil alignment workaround.Eric Anholt2012-12-221-0/+16
* i965/gen4-5: Fix segfaults with stencil-only depth/stencil setups.Eric Anholt2012-11-281-1/+3
* i965: Use the separate stencil buffer's offsets for stencil setup.Eric Anholt2012-11-191-15/+38
* i965: Move all the depth/stencil/hiz offset logic into the workaround.Eric Anholt2012-11-191-108/+113
* i965: When rebasing depth or stencil, update x/y before deciding the other.Eric Anholt2012-11-191-13/+36
* i965/gen4: Fix assertion failures in depthstencil piglit tests.Eric Anholt2012-11-011-4/+5
* i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt.Eric Anholt2012-10-161-61/+126
* i965: Share the draw x/y offset masking code between main/blorp and all gens.Eric Anholt2012-10-161-41/+70
* intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.Paul Berry2012-09-121-2/+3
* intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.Paul Berry2012-09-121-3/+3
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-2/+4
* i965/gen6: Initial implementation of MSAA.Paul Berry2012-05-151-25/+8
* i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-071-0/+36
* i965: Fix mipmap offsets for HiZ and separate stencil buffers.Paul Berry2012-05-071-8/+88
* intel: use _mesa_is_winsys/user_fbo() helpersBrian Paul2012-05-011-9/+9
* i965: Stop lying about cpp and height of a stencil buffer.Paul Berry2012-04-101-5/+6
* i965: Fix Gen6+ dynamic state upper bound on older kernels.Kenneth Graunke2012-02-291-2/+1
* i965: Rename the original binding table to mention that it's the WM now.Eric Anholt2012-02-211-2/+2
* i965: Split the gen6 GS binding table to a separate table.Eric Anholt2012-02-211-1/+1
* i965: Split the VS binding table to a separate table.Eric Anholt2012-02-211-2/+2
* i965: Fix border color on Ironlake.Kenneth Graunke2012-02-101-1/+1
* intel: derive intel_renderbuffer from swrast_renderbufferBrian Paul2012-01-241-4/+4
* intel: use intel_rb_format() to get renderbuffer formatBrian Paul2012-01-241-3/+3
* i965: Fix border color on Sandybridge and Ivybridge.Kenneth Graunke2012-01-231-1/+7
* i965/gen5: Fix rendering of depth buffers without stencil [v2]Chad Versace2012-01-171-2/+15
* i965/gen7: Fix depth buffer rendering to tile offsets.Eric Anholt2012-01-121-2/+2
* i965: Fix compiler warnings from hiz changes.Eric Anholt2012-01-101-2/+0
* i965: Replace references to stencil region size with buffer sizeChad Versace2012-01-101-4/+4
* i965: Correct misspellings of "invariant".Kenneth Graunke2012-01-071-4/+4
* i965: Don't use BRW_DEPTHFORMAT_D24_UNORM_X8_UINT on Gen4.Kenneth Graunke2011-12-231-1/+4
* i965 gen6: Initial implementation of transform feedback.Paul Berry2011-12-201-1/+1
* i965: Add support for GL_ARB_depth_buffer_float under 3.0 override.Eric Anholt2011-12-191-1/+4
* i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.Eric Anholt2011-12-191-1/+1
* intel: Stop creating the wrapped stencil irb.Eric Anholt2011-12-191-17/+23
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* i965: Base HW depth format setup based on MESA_FORMAT, not bpp.Eric Anholt2011-11-291-19/+32
* i965/gen6: Fix GPU hang when using stencil buffer without depthChad Versace2011-11-231-0/+5
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