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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
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* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-2/+4
* i965/gen6: Initial implementation of MSAA.Paul Berry2012-05-151-25/+8
* i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-071-0/+36
* i965: Fix mipmap offsets for HiZ and separate stencil buffers.Paul Berry2012-05-071-8/+88
* intel: use _mesa_is_winsys/user_fbo() helpersBrian Paul2012-05-011-9/+9
* i965: Stop lying about cpp and height of a stencil buffer.Paul Berry2012-04-101-5/+6
* i965: Fix Gen6+ dynamic state upper bound on older kernels.Kenneth Graunke2012-02-291-2/+1
* i965: Rename the original binding table to mention that it's the WM now.Eric Anholt2012-02-211-2/+2
* i965: Split the gen6 GS binding table to a separate table.Eric Anholt2012-02-211-1/+1
* i965: Split the VS binding table to a separate table.Eric Anholt2012-02-211-2/+2
* i965: Fix border color on Ironlake.Kenneth Graunke2012-02-101-1/+1
* intel: derive intel_renderbuffer from swrast_renderbufferBrian Paul2012-01-241-4/+4
* intel: use intel_rb_format() to get renderbuffer formatBrian Paul2012-01-241-3/+3
* i965: Fix border color on Sandybridge and Ivybridge.Kenneth Graunke2012-01-231-1/+7
* i965/gen5: Fix rendering of depth buffers without stencil [v2]Chad Versace2012-01-171-2/+15
* i965/gen7: Fix depth buffer rendering to tile offsets.Eric Anholt2012-01-121-2/+2
* i965: Fix compiler warnings from hiz changes.Eric Anholt2012-01-101-2/+0
* i965: Replace references to stencil region size with buffer sizeChad Versace2012-01-101-4/+4
* i965: Correct misspellings of "invariant".Kenneth Graunke2012-01-071-4/+4
* i965: Don't use BRW_DEPTHFORMAT_D24_UNORM_X8_UINT on Gen4.Kenneth Graunke2011-12-231-1/+4
* i965 gen6: Initial implementation of transform feedback.Paul Berry2011-12-201-1/+1
* i965: Add support for GL_ARB_depth_buffer_float under 3.0 override.Eric Anholt2011-12-191-1/+4
* i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.Eric Anholt2011-12-191-1/+1
* intel: Stop creating the wrapped stencil irb.Eric Anholt2011-12-191-17/+23
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* i965: Base HW depth format setup based on MESA_FORMAT, not bpp.Eric Anholt2011-11-291-19/+32
* i965/gen6: Fix GPU hang when using stencil buffer without depthChad Versace2011-11-231-0/+5
* intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]Chad Versace2011-11-221-2/+3
* intel: Replace intel_renderbuffer::region with a miptree [v3]Chad Versace2011-11-211-6/+15
* i965: Use a single binding table for all pipeline stages.Kenneth Graunke2011-11-101-4/+4
* i965: Remove the validated BO list, now that it's unused.Eric Anholt2011-10-291-17/+0
* intel: Rename region->buffer to region->bo, and remove accessor function.Eric Anholt2011-09-261-6/+6
* i965: Emit depth stalls and flushes before changing depth state on Gen6+.Kenneth Graunke2011-09-261-1/+3
* i965: Fix polygon stipple offset state flagging.Eric Anholt2011-09-201-4/+6
* i965: Add missing _NEW_POLYGON flag to polygon stipple upload.Eric Anholt2011-09-201-1/+3
* i965: Fix regression in 29a911c50e4443dfebef0a2e32c39b64992fa3cc.Eric Anholt2011-07-191-1/+1
* i965: Rename 3DSTATE_DRAWRECT_INFO_I965 to 3DSTATE_DRAWING_RECTANGLE.Kenneth Graunke2011-07-181-1/+1
* i965: Convert system instruction pointer to OUT_BATCH style.Kenneth Graunke2011-07-071-13/+4
* i965: Convert PIPELINE_SELECT to OUT_BATCH style.Kenneth Graunke2011-07-071-10/+4
* i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.Kenneth Graunke2011-07-071-10/+4
* i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.Kenneth Graunke2011-07-071-10/+5
* i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.Eric Anholt2011-06-281-9/+46
* i965/gen6: Add a couple more packets to the nonpipelined workaround list.Eric Anholt2011-06-231-0/+6
* i965/gen6: Apply documented workaround for nonpipelined state packets.Eric Anholt2011-06-201-0/+23
* i965: Use state streaming on programs, and state base address on gen5+.Eric Anholt2011-06-181-3/+7
* i965/gen5,6: Fix hang when emitting hiz buffer without stencil bufferChad Versace2011-06-151-18/+40
* intel: Move the draw_x/draw_y to the renderbuffer where it belongs.Eric Anholt2011-06-131-1/+1
* i965/brw: Fix emit_depthbuffer() when packed depth/stencil texture is attachedChad Versace2011-06-101-11/+5
* i965/gen7: Don't emit 3DSTATE_GS_SVB_INDEX on Ivybridge.Kenneth Graunke2011-06-081-7/+9
* i965/brw: Emit state for hiz and separate stencil buffersChad Versace2011-06-081-9/+105
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