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path: root/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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* i965: Unroll SIMD16 DDY_FINE on Sandybridge.Kenneth Graunke2016-04-251-1/+5
* i965/blorp: Prepare render target write for gen8Topi Pohjolainen2016-04-211-4/+5
* i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardwareJason Ekstrand2016-04-141-13/+62
* i965/fs: Don't force MASK_DISABLE on INDIRECT_MOV instructionsJason Ekstrand2016-04-141-1/+0
* i965/fs: Set exec size for gen7 pull const loadsIago Toral Quiroga2016-03-171-0/+1
* i965: Set dest type to UW for several send messagesJordan Justen2016-02-261-1/+1
* i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-091-1/+1
* i965/fs: Separate the sampler from the surface in generate_texJason Ekstrand2016-02-091-6/+14
* i965/fs: Implement support for extract_word.Matt Turner2016-02-011-0/+22
* i965/fs: Always set channel 2 of texture headers in some stagesJason Ekstrand2016-01-151-0/+8
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-151-3/+4
* i965: Drop extra newline from shader compile messages.Matt Turner2016-01-131-1/+1
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-2/+0
* i965: Push down inclusion of brw_program.h.Matt Turner2015-11-241-0/+1
* i965: Prevent implicit upcasts to brw_reg.Matt Turner2015-11-241-1/+1
* i965/fs: Stomp the texture return type to UINT32 for resinfo messagesJason Ekstrand2015-11-231-0/+11
* i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.Matt Turner2015-11-191-31/+1
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-141-0/+34
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-131-0/+4
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-131-1/+1
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-131-2/+5
* i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-2/+2
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-4/+4
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-131-6/+3
* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-131-6/+6
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-131-2/+3
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-131-20/+22
* i965: Add initial assembly validation pass.Matt Turner2015-11-121-0/+8
* i965: Set annotation_info's mem_ctx.Matt Turner2015-11-121-1/+1
* i965/fs: Do not mark used surfaces in FS_OPCODE_GET_BUFFER_SIZEIago Toral Quiroga2015-11-051-2/+0
* i965/fs: Do not mark used direct surfaces in UNIFORM_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-051-10/+0
* i965/fs: Do not mark direct used surfaces in VARYING_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-051-8/+0
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+5
* i965: Replace default case with list of enum values.Matt Turner2015-11-021-2/+7
* i965: dump scheduling cycle estimatesConnor Abbott2015-10-301-5/+6
* i965/fs: Emit a single ADD instruction for SET_SAMPLE_ID on Gen8+.Matt Turner2015-10-221-1/+1
* i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID.Matt Turner2015-10-221-5/+5
* i965/fs: Use type-W for immediate in SampleID setup.Matt Turner2015-10-221-1/+1
* i965: Implement ARB_shader_stencil_export (gen9+)Ben Widawsky2015-10-211-0/+53
* i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.Kenneth Graunke2015-10-211-0/+26
* i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.Kenneth Graunke2015-10-211-0/+11
* i965/fs: Remove the gl_program from the generatorJason Ekstrand2015-10-191-2/+1
* i965/asm: Explicitly use a nir_instr for IR annotationsJason Ekstrand2015-10-191-1/+1
* i965/fs: Handle non-const sample number in interpolateAtSampleNeil Roberts2015-10-091-3/+2
* i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+47
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-211-6/+6
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-211-1/+4
* i965: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-09-211-0/+2
* i965: add support for textureSamples functionIlia Mirkin2015-09-101-0/+4
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