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path: root/src/mesa/drivers/dri/i965/brw_fs.cpp
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* i965: Make uniform offsets be in terms of bytesJason Ekstrand2015-12-071-3/+1
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-071-8/+8
* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-301-0/+65
* i965: Fix fragment shader struct inputs.Kenneth Graunke2015-11-251-78/+79
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-13/+0
* i965: Compile brw_cs_fill_local_id_payload() as C.Matt Turner2015-11-241-36/+0
* i965: Push down inclusion of brw_program.h.Matt Turner2015-11-241-0/+1
* i965: Prevent implicit upcasts to brw_reg.Matt Turner2015-11-241-1/+2
* i965: Use scope operator to ensure brw_reg is interpreted as a type.Matt Turner2015-11-241-1/+1
* i965: Add and use backend_reg::equals().Matt Turner2015-11-241-2/+1
* i965: Use nir_lower_tex for texture coordinate loweringJason Ekstrand2015-11-231-0/+4
* i965: Move postprocess_nir to codegen timeJason Ekstrand2015-11-231-2/+9
* i965/fs: print non-1 strides when dumping instructionsConnor Abbott2015-11-231-0/+12
* i965/fs: Replace fs_reg(imm) constructors with brw_imm_*().Matt Turner2015-11-191-74/+26
* i965: Allow indirect GS input indexing in the scalar backend.Kenneth Graunke2015-11-181-17/+0
* i965: Add assertion for src_stencil payload sizeBen Widawsky2015-11-171-0/+6
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-141-0/+28
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-131-0/+2
* i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
* i965: Combine register file field.Matt Turner2015-11-131-3/+2
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-131-67/+53
* i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-52/+52
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-82/+81
* i965: Unwrap some lines.Matt Turner2015-11-131-4/+1
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-131-48/+45
* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-131-40/+40
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-131-37/+37
* i965: Print force_writemask_all in dump_instructions().Kenneth Graunke2015-11-111-0/+3
* i965: Fix scalar VS float[] and vec2[] output arrays.Kenneth Graunke2015-11-051-0/+13
* i965/fs: Do not mark used direct surfaces in UNIFORM_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-051-1/+1
* i965/fs: Do not mark direct used surfaces in VARYING_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-051-3/+4
* i965/fs/skl+: Fix calculating gl_SampleID for 16x MSAANeil Roberts2015-11-051-1/+7
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-2/+40
* i965: Add scalar geometry shader support.Kenneth Graunke2015-11-031-14/+194
* i965: Replace default case with list of enum values.Matt Turner2015-11-021-10/+3
* i965/fs: move the fs_reg::smear() from get_timestamp() to the callersEmil Velikov2015-10-301-12/+17
* i965: always run the post-RA schedulerConnor Abbott2015-10-301-2/+1
* i965/fs: Use group(4, 0) to emit an exec-size 4 MOV.Matt Turner2015-10-291-2/+3
* i965: Implement ARB_fragment_layer_viewport.Kenneth Graunke2015-10-281-1/+6
* i965/fs: Properly check for PAD in fragment shaders with > 16 varyings.Kenneth Graunke2015-10-281-4/+1
* i965/fs: Use unsigned immediate 0 when eliminating SHADER_OPCODE_FIND_LIVE_CH...Kristian Høgsberg Kristensen2015-10-231-1/+1
* i965: Don't use message headers for untyped readsKristian Høgsberg Kristensen2015-10-231-1/+1
* i965/fs: Trim unneeded channels in SampleID setup.Matt Turner2015-10-221-6/+6
* i965/fs: Use type-W for immediate in SampleID setup.Matt Turner2015-10-221-2/+2
* i965: Implement ARB_shader_stencil_export (gen9+)Ben Widawsky2015-10-211-0/+14
* i965/fs: Enumerate logical fb writes argumentsBen Widawsky2015-10-211-12/+15
* i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.Kenneth Graunke2015-10-211-0/+2
* i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.Kenneth Graunke2015-10-211-0/+9
* i965/fs: Disable opt_sampler_eot for more message typesNeil Roberts2015-10-211-6/+8
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